Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

Abstract: A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: A bus interface bus is described. A first logical state is conveyed over the bus by a higher voltage level and a second logical state is conveyed by a lower voltage level. An output stage of the interface includes a power transistor configured to drive the lower voltage level onto the bus to convey the second logical state, and a protective device between the power transistor and the bus. The protective device couples the power transistor to the bus when turned on and limits negative voltage excursions at the power transistor when turned off. A control circuit of the interface is configured to turn on the protective device when the bus voltage is above the lower voltage level and to turn off the protective device when the bus voltage is at or below the lower voltage level.

Abstract: A control device for controlling an engine provided with a fuel pump including a pressurizing chamber, a plunger inserted into the pressurizing chamber and which changes a volume of the pressurizing chamber, and an on-off valve configured to open and close a suction port, is provided. When a pressurizing cycle consists of a period of pressurizing stroke in which the volume of the pressurizing chamber is reduced to allow fuel to be pressurized and a period of suction stroke in which the volume of the pressurizing chamber is increased to allow fuel to be drawn into the pressurizing chamber, a closing cycle of the on-off valve is controlled so that a ratio of the closing cycle to the pressurizing cycle becomes smaller in a second combustion mode where a partial compression-ignition combustion is performed than in a first combustion mode where SI combustion is performed.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: A control device for controlling an engine provided with a fuel pump including a pressurizing chamber, a plunger inserted into the pressurizing chamber and which changes a volume of the pressurizing chamber, and an on-off valve configured to open and close a suction port, is provided. When a pressurizing cycle consists of a period of pressurizing stroke in which the volume of the pressurizing chamber is reduced to allow fuel to be pressurized and a period of suction stroke in which the volume of the pressurizing chamber is increased to allow fuel to be drawn into the pressurizing chamber, a closing cycle of the on-off valve is controlled so that a ratio of the closing cycle to the pressurizing cycle becomes smaller in a second combustion mode where a partial compression-ignition combustion is performed than in a first combustion mode where SI combustion is performed.

Abstract: Systems and methods for driving a low quiescent current DCDC converter are disclosed. An error threshold compensation circuit of the DCDC converter is configured to detect an output voltage of the DCDC converter, compare the output voltage to a target voltage, and modify a first threshold voltage of the hysteresis control circuit based on the comparison.

Abstract: Disclosed herein are an apparatus for controlling a switch-mode power supply, and a method of operating the same. In an embodiment, it is determined whether or not a current of an inductor of the switching power supply has become less than or equal to a predetermined value. In an embodiment, a variable reference voltage is adjusted based on the current of the inductor and an output voltage. In an embodiment, a switch is turned off based on the inductor current, the output voltage, and the variable reference voltage.

Abstract: Systems and methods for driving a low quiescent current DCDC converter are disclosed. An error threshold compensation circuit of the DCDC converter is configured to detect an output voltage of the DCDC converter, compare the output voltage to a target voltage, and modify a first threshold voltage of the hysteresis control circuit based on the comparison.

Abstract: In a structure for mounting, on a cylinder block, a fuel pump including a fuel pump drive shaft which is rotated by receiving a driving force of a crankshaft, and a fuel pump body which is operated as the fuel pump drive shaft is rotated for pumping fuel, the cylinder block includes a flange portion, on an end portion of the cylinder block in the crankshaft direction, projecting from a surface of the end portion along the crankshaft direction in a direction orthogonal to the crankshaft direction. The flange portion includes a bearing portion which rotatably supports the fuel pump drive shaft, and a pump accommodating hole portion which accommodates the fuel pump body. The fuel pump drive shaft is rotatably supported on the bearing portion, and the fuel pump body is accommodated in the pump accommodating hole portion.

Abstract: In a structure for mounting, on a cylinder block, a fuel pump including a fuel pump drive shaft which is rotated by receiving a driving force of a crankshaft, and a fuel pump body which is operated as the fuel pump drive shaft is rotated for pumping fuel, the cylinder block includes a flange portion, on an end portion of the cylinder block in the crankshaft direction, projecting from a surface of the end portion along the crankshaft direction in a direction orthogonal to the crankshaft direction. The flange portion includes a bearing portion which rotatably supports the fuel pump drive shaft, and a pump accommodating hole portion which accommodates the fuel pump body. The fuel pump drive shaft is rotatably supported on the bearing portion, and the fuel pump body is accommodated in the pump accommodating hole portion.

Abstract: A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided.

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract: A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an offset voltage Voffset which becomes smaller depending on the ON period Ton in excess of ½ of an operating cycle T, to a coil current waveform Vsense.

Abstract: A DC-DC converter includes an input terminal Pin receiving an voltage input, switching circuits connected in parallel between the input terminal Pin and ground, an output terminal Pout from which converted voltage is output, and a controller that turns the switching circuits on in a predetermined cycle by inputting, into each of the switching circuits, a control signal that turns the switching circuits on individually.