Patents by Inventor Toru Mogami

Toru Mogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010053601
    Abstract: According to a method of manufacturing a MIS semiconductor device of the present invention, a gate insulating film is formed on a silicon substrate, and a silicon thin film is deposited on the gate insulating film, whereafter a silicon film containing germanium is deposited on the silicon thin film and an amorphous silicon film is deposited on the germanium-containing silicon film. Further, heat treatment is performed to diffuse the germanium in the germanium-containing silicon film into the silicon thin film, and a metal film is deposited on the amorphous silicon film and heat treatment is performed to cause a silicidation reaction to occur with the metal film to form a silicide film. Therefore, the germanium-containing silicon film which can control gate depletion can be formed stably with a good reproducibility. Further, since the silicide film on the gate electrode is formed on the silicon film, it can be formed with a low resistance.
    Type: Application
    Filed: May 8, 2001
    Publication date: December 20, 2001
    Inventor: Toru Mogami
  • Patent number: 6197661
    Abstract: A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised ofa semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: March 6, 2001
    Assignee: NEC Corporation
    Inventors: Toru Mogami, Takashi Ogura
  • Patent number: 6027977
    Abstract: A fabrication method of a semiconductor device with the MIS structure is provided, which prevents the boron penetration phenomenon from occurring even if a gate insulator film is as thin as approximately 3 nm or less. After a silicon nitride film is formed on a semiconductor substrate, oxygen is doped into the silicon nitride film by a suitable process such as a thermal oxidation, ion implantation or plasma doping process, thereby forming an oxygen-doped silicon nitride film having an oxygen-rich region that extends along an interface between the oxygen-doped silicon nitride film and the substrate. The oxygen-rich region is higher in oxygen concentration than the remainder of the oxygen-doped silicon nitride film. At least part of the oxygen-doped silicon nitride film serves as a gate insulator film of a MISFET. Next, a gate electrode of the MISFET is formed on the oxygen-doped silicon nitride film.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Toru Mogami
  • Patent number: 5929504
    Abstract: A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised of a semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: July 27, 1999
    Assignee: NEC Corporation
    Inventors: Toru Mogami, Takashi Ogura