Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: An information processing apparatus having an input device for receiving data, an operation unit for constituting a convolutional neural network for processing data, a storage area for storing data to be used by the operation unit and an output device for outputting a result of the processing. The convolutional neural network is provided with a first intermediate layer for performing a first processing including a first inner product operation and a second intermediate layer for performing a second processing including a second inner product operation, and is configured so that the bit width of first filter data for the first inner product operation and the bit width of second filter data for the second inner product operation are different from each other.

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Abstract: In a processing method using a convolutional neural network, the neural network includes a convolution calculation unit that performs a convolution calculation by using a matrix vector product and a pooling calculation unit that performs a maximum value sampling calculation. A threshold value is set related to the matrix data for the convolution calculation, the matrix data is divided into a first and second halves based on the threshold value. The convolution calculation unit divides a first half convolution calculation by using the first half of the matrix data and a second half convolution calculation by using the second half of the matrix data into two and executes the calculations. The pooling calculation unit selects vector data to which the matrix vector product convolution calculation is to be performed in the second half convolution calculation, along with the maximum value sampling calculation.

Abstract: An information processing apparatus having an input device for receiving data, an operation unit for constituting a convolutional neural network for processing data, a storage area for storing data to be used by the operation unit and an output device for outputting a result of the processing. The convolutional neural network is provided with a first intermediate layer for performing a first processing including a first inner product operation and a second intermediate layer for performing a second processing including a second inner product operation, and is configured so that the bit width of first filter data for the first inner product operation and the bit width of second filter data for the second inner product operation are different from each other.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.