Patents by Inventor Toru Muramatsu

Toru Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299077
    Abstract: A semiconductor device includes a semiconductor substrate that has a transistor portion and a diode portion and that is provided with a plurality of trench portions, in which the transistor portion has a main region that has the emitter region and the contact region at the front surface of the semiconductor substrate and that is spaced apart from the diode portion and a first boundary region that is provided between the main region and the diode portion and that has, at the front surface of the semiconductor substrate, the emitter region and the base region which are alternately provided in a trench extension direction.
    Type: Application
    Filed: January 23, 2023
    Publication date: September 21, 2023
    Inventors: Toru MURAMATSU, Tatsuya NAITO
  • Patent number: 10205010
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hong-fei Lu, Haruo Nakazawa
  • Publication number: 20180269314
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Toru MURAMATSU, Hong-fei LU, Haruo NAKAZAWA
  • Patent number: 10026831
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hong-fei Lu, Haruo Nakazawa
  • Patent number: 9608073
    Abstract: Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hiroki Wakimoto
  • Publication number: 20170054008
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Application
    Filed: August 10, 2016
    Publication date: February 23, 2017
    Inventors: Toru MURAMATSU, Hong-fei LU, Haruo NAKAZAWA
  • Publication number: 20160141364
    Abstract: Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 19, 2016
    Inventors: Toru MURAMATSU, Hiroki WAKIMOTO
  • Patent number: 9214304
    Abstract: A switch unit includes an operating component, and a base portion that supports the operating component capable of being pressed in criss-cross directions. The base portion is provided with a plurality of T-shaped regulating components that are formed in positions in directions sandwiched between the criss-cross directions. Each of the regulating components is provided with a leg portion that extends from the base portion towards the operating component, and an abutting portion that extends from an end portion of the leg portion along a line that connects together predetermined positions of the criss-cross directions that are located on both sides of each regulating component.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 15, 2015
    Assignees: HONDA MOTOR CO., LTD., TOYO DENSO CO., LTD.
    Inventors: Takuya Matsumoto, Masahiko Shimada, Kazunaga Kasai, Toru Muramatsu, Masahito Kobayashi
  • Publication number: 20130008766
    Abstract: A switch unit includes an operating component, and a base portion that supports the operating component capable of being pressed in criss-cross directions. The base portion is provided with a plurality of T-shaped regulating components that are formed in positions in directions sandwiched between the criss-cross directions. Each of the regulating components is provided with a leg portion that extends from the base portion towards the operating component, and an abutting portion that extends from an end portion of the leg portion along a line that connects together predetermined positions of the criss-cross directions that are located on both sides of each regulating component.
    Type: Application
    Filed: March 29, 2011
    Publication date: January 10, 2013
    Inventors: Takuya Matsumoto, Masahiko Shimada, Kazunaga Kasai, Toru Muramatsu, Masahito Kobayashi
  • Patent number: 8143539
    Abstract: An operation lever comprises a main section, a cover section and a photoconductor. While the photoconductor is overlaid on the main section, sliding protrusions of the cover section are inserted into guide grooves formed in the periphery of the main section, the cover section is slidingly pushed to insert a tip end section of the cover section inside an overhanging fringe of the main section. An engaging protrusion and an engaging pawl of the cover section are engaged with the main section to assemble the operation lever.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 27, 2012
    Assignee: Toyo Denso Kabushiki Kaisha
    Inventors: Toru Muramatsu, Masahito Kobayashi
  • Publication number: 20090127079
    Abstract: An operation lever comprises a main section, a cover section and a photoconductor. While the photoconductor is overlaid on the main section, sliding protrusions of the cover section are inserted into guide grooves formed in the periphery of the main section, the cover section is slidingly pushed to insert a tip end section of the cover section inside an overhanging fringe of the main section. An engaging protrusion and an engaging pawl of the cover section are engaged with the main section to assemble the operation lever.
    Type: Application
    Filed: November 14, 2008
    Publication date: May 21, 2009
    Applicant: Toyo Denso Kabushiki Kaisha
    Inventors: Toru Muramatsu, Masahito Kobayashi
  • Patent number: 5773281
    Abstract: Water contained in raw garbage introduced through a throw port is drained off by a filter member and a water-draining gate, and is drained into a drainpipe, the water having good quality. The raw garbage from which water is drained off to a sufficient degree is dry-pulverized by a pulverizer unit and is smoothly blown into the microorganism decomposition chamber through a carrier duct having a flared end, utilizing the impact force of the impeller revolving in the pulverizer unit. The dry-pulverized raw garbage that is thus conveyed is decomposed by a microorganism carrier in the microorganism decomposition chamber.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: June 30, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Masaya Ichikawa, Junichi Ooki, Toru Muramatsu
  • Patent number: 5240177
    Abstract: A ventilation apparatus for a container for transporting goods by truck or ship. The walls of the container are provided with an inlet opening and an outlet opening, and an inlet unit is connected to the inlet opening and an outlet unit is connected to the outlet opening. The outlet unit is provided with a battery-operated fan for a forced ventilation of the container, temperature sensors are provided for detecting the inner wall temperature and inner air temperature, and a degree of change in the wall temperature per unit of time is calculated for operating the fan when the degree of change in the wall temperature is larger than a predetermined value. Furthermore, the difference between the inner air temperature and the wall temperature is calculated, and the fan is operated when that difference is larger than a predetermined value.
    Type: Grant
    Filed: December 27, 1991
    Date of Patent: August 31, 1993
    Assignees: Nippondenso Co., Ltd., Mitsui O.S.K. Lines Ltd.
    Inventors: Toru Muramatsu, Naomi Kokubo, Kazuyuki Ouchi, Fuminobu Kondoh