Patents by Inventor Toru Nagamine
Toru Nagamine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082603Abstract: A time required for online adaptive treatment is reduced with a workflow management system that executes a plurality of processes for radiotherapy according to a predetermined workflow. The plurality of processes include at least a first process and a second process, and the workflow management system executes the following modules, in parallel, including a first module that is included in the first process, displays a result of a first calculation based on a patient image captured during treatment by an imaging apparatus that captures a predetermined region of a patient, and requests an input from an operator; and a second module that is included in the second process, and executes a second calculation based on the patient image during the treatment.Type: ApplicationFiled: August 10, 2021Publication date: March 14, 2024Inventors: Takahiro YAMADA, Yusuke FUJII, Toru UMEKAWA, Yoshihiko NAGAMINE, Takao KIDANI
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Patent number: 8471379Abstract: A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.Type: GrantFiled: January 31, 2012Date of Patent: June 25, 2013Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Publication number: 20120126900Abstract: A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Inventors: Tadatoshi DANNO, Toru NAGAMINE, Hiroshi MORI, Tsukasa ICHINOSE
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Patent number: 8115295Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: GrantFiled: February 3, 2011Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Patent number: 7982301Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: GrantFiled: September 15, 2009Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Publication number: 20110121443Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: ApplicationFiled: February 3, 2011Publication date: May 26, 2011Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Publication number: 20100001393Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: ApplicationFiled: September 15, 2009Publication date: January 7, 2010Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Patent number: 7608922Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: GrantFiled: May 27, 2005Date of Patent: October 27, 2009Assignee: Renesas Technology Corp.Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Publication number: 20050263881Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: ApplicationFiled: May 27, 2005Publication date: December 1, 2005Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Patent number: 6710429Abstract: A semiconductor device is provided with outer leads which show themselves in the bottom surface of the resin encapsulated body. This structure eliminates minute chipping and cracking near the resin which has been cut in the vicinity of the end of the outer lead. The semiconductor device is produced in such a way that a push-back-portion is previously arranged between leads of the lead frame and the push-back-portion is pushed down after molding. The resulting semiconductor device has outer leads such that there is no encapsulating resin between outer leads which show themselves in the bottom surface of the resin encapsulated body.Type: GrantFiled: June 18, 2001Date of Patent: March 23, 2004Assignee: Renesas Technology Corp.Inventors: Masahiro Saito, Toru Nagamine, Ichio Shimizu
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Publication number: 20020000674Abstract: A semiconductor device is provided with outer leads which show themselves in the bottom surface of the resin encapsulated body. This structure eliminates minute chipping and cracking near the resin which has been cut in the vicinity of the end of the outer lead. The semiconductor device is produced in such a way that a push-back-portion is previously arranged between leads of the lead frame and the push-back-portion is pushed down after molding. The resulting semiconductor device has outer leads such that there is no encapsulating resin between outer leads which show themselves in the bottom surface of the resin encapsulated body.Type: ApplicationFiled: June 18, 2001Publication date: January 3, 2002Inventors: Masahiro Saito, Toru Nagamine, Ichio Shimizu