Patents by Inventor Toru Nasu

Toru Nasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090321801
    Abstract: A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation.
    Type: Application
    Filed: September 3, 2009
    Publication date: December 31, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Shinichiro HAYASHI, Toru Nasu
  • Patent number: 7603423
    Abstract: When a mail server 31 and a mail server 32 are in a failover state, switches 21, 22 select communication paths E, F. A temporary save server 50 stores email received from a mail reception server 10 during the failover in a disk storage 60, and after the completion of the failover, transmits to a mail server (e.g., mail server 32) that has been switched to function as a primary system an email stored in disk storage 60 and a write request for a disk storage 40. Mail server 32, upon receiving an email and a write request from temporary save server 50, stores the received email to disk storage 40 to update stored content.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: October 13, 2009
    Assignee: NTT DoCoMo, Inc.
    Inventors: Takayuki Ito, Hidenori Miyamoto, Toru Nasu, Shikiko Kawano
  • Patent number: 7304341
    Abstract: A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating film of a dielectric film formed on wall and bottom portions of the second recess and having a third recess, and a capacitor upper electrode formed on wall and bottom portions of the third recess; and a conductive layer (referred hereinafter to as a low-resistance conductive layer) which is formed to cover at least portions of the respective capacitor upper electrodes constituting the plurality of capacitor elements and to extend across the plurality of capacitor elements and which has a lower resistance than the capacitor upper electrode.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: December 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takumi Mikawa, Toru Nasu
  • Publication number: 20070161126
    Abstract: In a ferroelectric capacitor comprising: a lower electrode; a ferroelectric film formed on the lower electrode; and an upper electrode formed on the ferroelectric film, the coercive voltage of the ferroelectric film is 1.5 V or less and the polarization switching time of the ferroelectric film is 200 ns or less.
    Type: Application
    Filed: October 2, 2006
    Publication date: July 12, 2007
    Inventors: Shinichiro Hayashi, Toru Nasu
  • Patent number: 7220598
    Abstract: A method of making a ferroelectric thin film includes the step of forming a ferroelectric thin film with a randomly oriented layered structure on a surface of a conductor layer. At least the surface of the conductor layer has a spherical crystal structure.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: May 22, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Nasu, Shinichiro Hayashi
  • Publication number: 20060292816
    Abstract: A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating film of a dielectric film formed on wall and bottom portions of the second recess and having a third recess, and a capacitor upper electrode formed on wall and bottom portions of the third recess; and a conductive layer (referred hereinafter to as a low-resistance conductive layer) which is formed to cover at least portions of the respective capacitor upper electrodes constituting the plurality of capacitor elements and to extend across the plurality of capacitor elements and which has a lower resistance than the capacitor upper electrode.
    Type: Application
    Filed: May 2, 2006
    Publication date: December 28, 2006
    Inventors: Takumi Mikawa, Toru Nasu
  • Publication number: 20060108621
    Abstract: A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation.
    Type: Application
    Filed: October 13, 2005
    Publication date: May 25, 2006
    Inventors: Shinichiro Hayashi, Toru Nasu
  • Publication number: 20060030057
    Abstract: A capacitive element comprises: a lower electrode formed above a semiconductor substrate; a capacitive insulating film formed of a ferroelectric on the lower electrode so as to have a thickness of 100 nm or less; and an upper electrode formed on the capacitive insulating element. In any cross section of the capacitive insulating film which is perpendicular to the semiconductor substrate, a sum of the widths of voids generated in the capacitive insulating film which are measured in a direction perpendicular to the thickness direction of the capacitive insulating film is 20% or less of a unit width.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 9, 2006
    Inventors: Shinichiro Hayashi, Toru Nasu
  • Publication number: 20060026250
    Abstract: When a mail server 31 and a mail server 32 are in a failover state, switches 21, 22 select communication paths E, F. A temporary save server 50 stores email received from a mail reception server 10 during the failover in a disk storage 60, and after the completion of the failover, transmits to a mail server (e.g., mail server 32) that has been switched to function as a primary system an email stored in disk storage 60 and a write request for a disk storage 40. Mail server 32, upon receiving an email and a write request from temporary save server 50, stores the received email to disk storage 40 to update stored content.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: Takayuki Ito, Hidenori Miyamoto, Toru Nasu, Shikiko Kawano
  • Publication number: 20050045990
    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 3, 2005
    Applicant: Matsushita Electronics Corporation
    Inventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
  • Patent number: 6809000
    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: October 26, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
  • Patent number: 6781179
    Abstract: The semiconductor memory device of the present invention includes: an interlayer insulating film formed on a semiconductor substrate; a contact plug formed to extend through the interlayer insulating film; and a capacitor formed on the interlayer insulating film so that an electrode of the capacitor is connected with the contact plug. The electrode has an iridium oxide film as an oxygen barrier film. The average grain size of granular crystals constituting the iridium oxide film is a half or less of the thickness of the iridium oxide film.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Nasu, Yoshihisa Nagano
  • Patent number: 6756621
    Abstract: The ferroelectric capacitor device includes a bottom electrode, a capacitor insulating film formed of a ferroelectric film, and a top electrode. The ferroelectric film has a bismuth layer structure including a plurality of bismuth oxide layers and a plurality of perovskite-like layers alternately put on top of each other. The plurality of bismuth oxide layers are formed of Bi2O2, and the plurality of perovskite-like layers include two or more kinds of layers represented by a general formula: Am−1BmO3m+&agr; (where A is a univalent, divalent or trivalent metal, B is a tetravalent, pentavalent or hexavalent metal, m is an integer equal to or more than 1, at least one of A being Bi if m is an integer of 2 or more, and 0≦&agr;≦1) and different in the value of m.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Nasu, Shinichiro Hayashi
  • Publication number: 20040104414
    Abstract: The ferroelectric capacitor device includes a bottom electrode, a capacitor insulating film formed of a ferroelectric film, and a top electrode. The ferroelectric film has a bismuth layer structure including a plurality of bismuth oxide layers and a plurality of perovskite-like layers alternately put on top of each other. The plurality of bismuth oxide layers are formed of Bi2O2, and the plurality of perovskite-like layers include two or more kinds of layers represented by a general formula: Am−1BmO3m+&agr; (where A is a univalent, divalent or trivalent metal, B is a tetravalent, pentavalent or hexavalent metal, m is an integer equal to or more than 1, at least one of A being Bi if m is an integer of 2 or more, and 0<&agr;<1) and different in the value of m.
    Type: Application
    Filed: December 30, 2002
    Publication date: June 3, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toru Nasu, Shinichiro Hayashi
  • Patent number: 6734456
    Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0<y≦(4−x)×0.1 and 0.5<z<1.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisuke Tanaka, Toru Nasu, Masamichi Azuma
  • Publication number: 20030151078
    Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0≦y≦(4−x)×0.1 and 0.5<z<1.
    Type: Application
    Filed: November 5, 2002
    Publication date: August 14, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisuke Tanaka, Toru Nasu, Masamichi Azuma
  • Patent number: 6528327
    Abstract: A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihisa Nagano, Toru Nasu, Hajime Yasuoka, Eiji Fujii
  • Patent number: 6528365
    Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihisa Nagano, Keisuke Tanaka, Toru Nasu
  • Publication number: 20020179947
    Abstract: The semiconductor memory device of the present invention includes: an interlayer insulating film formed on a semiconductor substrate; a contact plug formed to extend through the interlayer insulating film; and a capacitor formed on the interlayer insulating film so that an electrode of the capacitor is connected with the contact plug. The electrode has an iridium oxide film as an oxygen barrier film. The average grain size of granular crystals constituting the iridium oxide film is a half or less of the thickness of the iridium oxide film.
    Type: Application
    Filed: May 23, 2002
    Publication date: December 5, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toru Nasu, Yoshihisa Nagano
  • Patent number: 6447838
    Abstract: A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: September 10, 2002
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Masamichi Azuma, Eiji Fujii, Yasuhiro Uemoto, Shinichiro Hayashi, Toru Nasu, Yoshihiro Shimada, Akihiro Matsuda, Tatsuo Otsuki, Michael C. Scott, Joseph D. Cuchiaro, Carlos A. Paz de Araujo