Patents by Inventor Toru Nimura

Toru Nimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240283220
    Abstract: A method for manufacturing a photonic crystal including forming a first layer, forming a first hole and a second hole, crystal-growing a second layer, to form, at the first hole, a first low refractive index portion, and form, at the second hole, a second low refractive index portion, wherein during formation of the first hole and the second hole, the first hole and the second hole are formed such that a diameter of the first hole is greater than a diameter of the second hole, and during formation of the first low refractive index portion and the second low refractive index portion, the second layer is crystal-grown such that a difference between the diameter of the first hole and a diameter of the first low refractive index portion is greater than a difference between the diameter of the second hole and a diameter of the second low refractive index portion.
    Type: Application
    Filed: February 19, 2024
    Publication date: August 22, 2024
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yoshitomo KUMAI, Toru NIMURA
  • Patent number: 10859882
    Abstract: A liquid crystal apparatus as an electro-optical device includes a TFT including a semiconductor layer and a gate electrode, a scan line electrically connected to the gate electrode and provided in a layer different from a layer where the gate electrode is provided, a capacitance line, and a conductive light shielding film electrically connected to the capacitance line. The light shielding film is provided in a layer between the gate electrode and the scan line, and in a plan view, overlaps with at least a part of a low-concentration drain region of the semiconductor layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toru Nimura, Hiroyuki Oikawa, Shinsuke Fujikawa
  • Publication number: 20200312890
    Abstract: In the electro-optical device, a gate electrode and a scanning line are electrically connected through a first contact hole disposed on the first insulating layer (interlayer insulating layer) overlapping the transistor. In a layer between the gate electrode and the scanning line, a first light shielding layer to which a constant potential is applied is disposed, and a light shielding portion electrically connected to the first light shielding layer covers a part of the semiconductor layer from both sides in a width direction. The light shielding portion includes a first portion that electrically connects the second light shielding layer and the first light shielding layer, and a second portion protruding from the first portion toward the semiconductor layer.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki OIKAWA, Toru NIMURA, Shinsuke FUJIKAWA
  • Patent number: 10620494
    Abstract: In an element substrate of an electro-optical device, a semiconductor layer of a transistor has an L shape bending to overlap with both a scanning line and a data line. A first light shielding layer overlaps with a lower layer side of the semiconductor layer. A first light shielding wall and a second light shielding wall are provided on both sides of a semiconductor layer portion between a channel region and a second source/drain region (drain region) of the semiconductor layer. The first light shielding wall and the second light shielding wall to which a constant potential is applied prevent the semiconductor layer portion from being electrically affected even when the first light shielding wall and the second light shielding wall come close to the semiconductor layer portion.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki Oikawa, Toru Nimura, Shinsuke Fujikawa
  • Publication number: 20190331972
    Abstract: A liquid crystal apparatus as an electro-optical device includes a TFT including a semiconductor layer and a gate electrode, a scan line electrically connected to the gate electrode and provided in a layer different from a layer where the gate electrode is provided, a capacitance line, and a conductive light shielding film electrically connected to the capacitance line. The light shielding film is provided in a layer between the gate electrode and the scan line, and in a plan view, overlaps with at least a part of a low-concentration drain region of the semiconductor layer.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toru NIMURA, Hiroyuki OIKAWA, Shinsuke FUJIKAWA
  • Publication number: 20190196281
    Abstract: In an element substrate of an electro-optical device, a semiconductor layer of a transistor has an L shape bending to overlap with both a scanning line and a data line. A first light shielding layer overlaps with a lower layer side of the semiconductor layer. A first light shielding wall and a second light shielding wall are provided on both sides of a semiconductor layer portion between a channel region and a second source/drain region (drain region) of the semiconductor layer. The first light shielding wall and the second light shielding wall to which a constant potential is applied prevent the semiconductor layer portion from being electrically affected even when the first light shielding wall and the second light shielding wall come close to the semiconductor layer portion.
    Type: Application
    Filed: December 26, 2018
    Publication date: June 27, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki OIKAWA, Toru NIMURA, Shinsuke FUJIKAWA
  • Patent number: 10241239
    Abstract: An element substrate is formed as a lens array substrate on which a plurality of lenses are formed. In a method of manufacturing the lens array substrate, first recess sections are formed on one surface of the substrate, and then a plurality of lens surfaces, which include concave surfaces, are formed at the bottoms of the first recess sections 195. Subsequently, after a light-transmitting lens layer is formed to fill the inside of the first recess sections, flattening is performed while the lens layer is removed. Here, the surface of the lens layer on a side opposite to the substrate is a planar surface which is contiguous to an outside area that is positioned on the outer side of the first recess sections on the one surface of the substrate.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 26, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Patent number: 10007033
    Abstract: A microlens array includes a first lens, a second lens, and a third lens. The first lens and the second lens are adjacent to each other and are arranged neighboring in a first direction. The first lens and the third lens are adjacent to each other and are arranged neighboring in a second direction substantially orthogonal to the first direction. A gap between an apex of the first lens and an apex of the second lens is different to a gap between the apex of the first lens and an apex of the third lens.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 26, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Patent number: 9983334
    Abstract: A micro lens array substrate includes a substrate including a plurality of concave portions arranged in a first direction and a second direction intersecting the first direction on one surface of the substrate, and a lens layer having a different refractive index from the substrate. The lens layer is formed on the one surface of the substrate to fill in the plurality of concave portions. The plurality of concave portions is continuous in at least one of the first direction and the second direction and is arranged to have a discontinuous part in the lens layer between two adjacent concave portions in a third direction intersecting the first and second directions. A first depth of a center of one concave portion from the discontinuous part is greater than a second depth of the discontinuous part from a surface of the lens layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 29, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Publication number: 20180045859
    Abstract: A micro lens array substrate includes a substrate including a plurality of concave portions arranged in a first direction and a second direction intersecting the first direction on one surface of the substrate, and a lens layer having a different refractive index from the substrate. The lens layer is formed on the one surface of the substrate to fill in the plurality of concave portions. The plurality of concave portions is continuous in at least one of the first direction and the second direction and is arranged to have a discontinuous part in the lens layer between two adjacent concave portions in a third direction intersecting the first and second directions. A first depth of a center of one concave portion from the discontinuous part is greater than a second depth of the discontinuous part from a surface of the lens layer.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventor: Toru Nimura
  • Patent number: 9829608
    Abstract: A micro lens array substrate includes a substrate having optical transparency and a lens layer having optical transparency and a different refractive index from that of the substrate, which is formed in such a manner as to fill in a concave portion arranged in one surface of the substrate in the X-direction, the Y-direction, and the W-direction. A through-hole is provided in the lens layer, between the adjacent concave portions in the W-direction in the lens layer, and the lens layer is continuous between the adjacent concave portions in the X-direction or in the Y-direction.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 28, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Publication number: 20170285396
    Abstract: In forming of an element substrate of an electro-optical device, after a plurality of films having a film that forms the pixel switching elements on one surface side of the substrate and a film that forms the pixel electrodes are formed, the substrate is removed through polishing and etching, and thus a layered structure is acquired. Subsequently, in pasting, a surface, on which the substrate is located, is pasted to a lens array substrate that is provided with a lens surface and a lens layer, which covers the lens surface, by an adhesive layer in the layered structure such that the pixel electrodes overlap the lens surface in plan view.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 5, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Toru NIMURA
  • Publication number: 20170285397
    Abstract: In a step of forming an element substrate of an electro-optical device, a layered structure, which includes a plurality of films having a film that forms pixel switching elements and a film that forms holding capacitors, is formed on one surface of the substrate, and, thereafter, a lens surface and a lens layer are formed on a second surface of the layered structure. Subsequently, after the substrate is removed by polishing and etching, pixel electrodes are formed on a side of a first substrate, on which the substrate is located, of the layered structure. Therefore, the holding capacitors are provided on a side opposite to a side of the pixel electrodes (side of a counter substrate) for the pixel switching elements.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 5, 2017
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Toru NIMURA
  • Publication number: 20170219744
    Abstract: An element substrate is formed as a lens array substrate on which a plurality of lenses are formed. In a method of manufacturing the lens array substrate, first recess sections are formed on one surface of the substrate, and then a plurality of lens surfaces, which include concave surfaces, are formed at the bottoms of the first recess sections 195. Subsequently, after a light-transmitting lens layer is formed to fill the inside of the first recess sections, flattening is performed while the lens layer is removed. Here, the surface of the lens layer on a side opposite to the substrate is a planar surface which is contiguous to an outside area that is positioned on the outer side of the first recess sections on the one surface of the substrate.
    Type: Application
    Filed: January 19, 2017
    Publication date: August 3, 2017
    Inventor: Toru Nimura
  • Publication number: 20170045647
    Abstract: A micro lens array substrate includes a substrate having optical transparency and a lens layer having optical transparency and a different refractive index from that of the substrate, which is formed in such a manner as to fill in a concave portion arranged in one surface of the substrate in the X-direction, the Y-direction, and the W-direction. A through-hole is provided in the lens layer, between the adjacent concave portions in the W-direction in the lens layer, and the lens layer is continuous between the adjacent concave portions in the X-direction or in the Y-direction.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Inventor: Toru Nimura
  • Publication number: 20170023707
    Abstract: A microlens array includes a first lens, a second lens, and a third lens. The first lens and the second lens are adjacent to each other and are arranged neighboring in a first direction. The first lens and the third lens are adjacent to each other and are arranged neighboring in a second direction substantially orthogonal to the first direction. A gap between an apex of the first lens and an apex of the second lens is different to a gap between the apex of the first lens and an apex of the third lens.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Inventor: Toru Nimura
  • Patent number: 9551896
    Abstract: A liquid crystal device includes a first substrate that is arranged on a light input side; a second substrate that is arranged on a light output side; a liquid crystal layer that is arranged between the first and second substrates; a first microlens that is provided on the first substrate such that an optical axis is tilted to a normal line direction of the first substrate; and a second microlens that is provided on the second substrate such that an optical axis is tilted to a normal line direction of the second substrate, in which a focal point of the first microlens is located on a curved surface of the second microlens, or on the light output side rather than the curved surface.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: January 24, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Patent number: 9500900
    Abstract: A micro lens array substrate includes a substrate having optical transparency and a lens layer having optical transparency and a different refractive index from that of the substrate, which is formed in such a manner as to fill in a concave portion arranged in one surface of the substrate in the X-direction, the Y-direction, and the W-direction. A through-hole is provided in the lens layer, between the adjacent concave portions in the W-direction in the lens layer, and the lens layer is continuous between the adjacent concave portions in the X-direction or in the Y-direction.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 22, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Patent number: 9477015
    Abstract: A microlens array includes a cell, and P lenses (P is an integer of 4 or more) arranged in the cell, in which the apexes of the P lenses are arranged such that symmetry is at least partially broken, when viewed in plan view. In this way, it is possible to suppress diffraction caused by regularity in the lens shape in the cell. Accordingly, it is possible to realize a microlens with a high utilization efficiency of light.
    Type: Grant
    Filed: December 13, 2014
    Date of Patent: October 25, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Publication number: 20160246119
    Abstract: An electro-optical device comprises a pair of substrates, a first microlens positioned at an inner side in a display region of at least one substrate of the pair of substrates, and a second microlens positioned further to an outer side in the display region of the at least one substrate than the first microlens. The collection efficiency of the first microlens is lower than the collection efficiency of the second microlens.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventor: Toru Nimura