Abstract: A computer system includes a plurality of computers and at least one storage connected to the plurality of computers. The storage includes a device that obtains information concerning areas within the storage that are used by the respective plurality of computers, a device that obtains information concerning a capacity within each of the areas that is used by each of the plurality of computers to store-data, and a device that notifies at least one of the plurality of computers of a status of the areas within the at least one storage. The computer system utilizes and manage the storage, without having each of the computers utilize and manage the storages with regard to storage capacity.

Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.

Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes.

Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.