Abstract: A first external connection terminal at a first row is disposed to position at upside of a first I/O cell, and a second external connection terminal at a second row is formed at upside of a boundary portion between two adjacent first I/O cells. Here, the first external connection terminal and the second external connection terminal are disposed to be separated for a predetermined distance so as not to have an overlapped portion with each other, and formed in an identical layer. According to the constitution, it is possible to prevent disadvantages such as characteristic deterioration of a semiconductor integrated circuit and accuracy deterioration of an electrical inspection.

Abstract: A first external connection terminal at a first row is disposed to position at upside of a first I/O cell, and a second external connection terminal at a second row is formed at upside of a boundary portion between two adjacent first I/O cells. Here, the first external connection terminal and the second external connection terminal are disposed to be separated for a predetermined distance so as not to have an overlapped portion with each other, and formed in an identical layer. According to the constitution, it is possible to prevent disadvantages such as characteristic deterioration of a semiconductor integrated circuit and accuracy deterioration of an electrical inspection.

Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.

Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.

Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.

Abstract: A semiconductor integrated circuit includes pads, a first power supply I/O cell which is connected to an external pin through a corresponding one of the pads, and a second power supply I/O cell which is not connected to an external pin through a corresponding one of the pads, but receives power supply from the first power supply I/O cell.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: A method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block includes the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.

Abstract: In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.

Abstract: A semiconductor integrated circuit device in which connections within and between logic unit cells can be efficiently made is provided. Logic unit cells each including a plurality of basic cells are extended in an X-direction. To form one logic unit cell, second-layer wiring regions for making connections within the logic unit cell are formed in the X-direction, i.e., the extending direction. If there are five Y-coordinate channels, the second-layer wiring regions are formed only at one Y-coordinate channel. Second-layer wiring regions for connecting logic unit cells are also formed in the X-direction, and can be situated at any of the remaining four Y-coordinate channels.

Abstract: A semiconductor integrated circuit device in which connections within and between logic unit cells can be efficiently made is provided. Logic unit cells each including a plurality of basic cells are extended in an X-direction. To form one logic unit cell, second-layer wiring regions for making connections within the logic unit cell are formed in the X-direction, i.e., the extending direction. If there are five Y-coordinate channels, the second-layer wiring regions are formed only at one Y-coordinate channel. Second-layer wiring regions for connecting logic unit cells are also formed in the X-direction, and can be situated at any of the remaining four Y-coordinate channels.

Abstract: A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site.

Abstract: A semiconductor integrated circuit includes pads, a first power supply I/O cell which is connected to an external pin through a corresponding one of the pads, and a second power supply I/O cell which is not connected to an external pin through a corresponding one of the pads, but receives power supply from the first power supply I/O cell.

Abstract: In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Abstract: A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site.

Abstract: A semiconductor device includes multi-pin I/O buffers. The I/O buffers are located near an I/O pad area of the device. The multi-pin I/O buffers include multiple, generally L-shaped terminals that are connected to pads in the I/O pad area with wirings. The terminals of the I/O buffers include a horizontal terminal section and a vertical terminal section. The horizontal terminal sections extend in a width direction from a corner of the buffer toward a middle point of a side of the buffer, and the vertical terminal section extends in a length direction from the corner of the terminal toward a middle point of a side of the buffer. The wirings may also be generally L-shaped.

Abstract: A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.