Abstract: A sampling data output circuit capable of Accommodating frequency variations includes a converter portion for sampling an input data signal (402) at an oversampling frequency to output, in parallel, a plurality of fundamental signal series (p1, p2, p3, p4), a first circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of first frequency shift signal series having a higher frequency than the fundamental sampling frequency, and a second circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of second frequency shift signal series having a lower frequency than the fundamental sampling frequency. The first and second circular shifters create each of the signal series by selecting a signal sample out of the input fundamental signal series according to a count value of a phase shift cumulative counter and a predetermined rule related to the frequency shift.

Abstract: A register unit that is capable of improving data security and minimizing the possibility of data alteration and other manipulations includes multiple registers and a bit layout circuit that is connected to the registers. The bit layout circuit stores a relationship table that defines the relationship between the register bit addresses of all the registers and designated bit addresses of addresses that are designated by an arithmetic unit for a read/write operation. Upon receipt of a write command and its data from the arithmetic unit, the bit layout circuit separates the data into bits, generates storage data by rearranging the data in compliance with the relationship table, and stores the generated data at the register bit addresses of registers indicated in the relationship table.

Abstract: A sampling data output circuit capable of Accommodating frequency variations includes a converter portion for sampling an input data signal (402) at an oversampling frequency to output, in parallel, a plurality of fundamental signal series (p1, p2, p3, p4), a first circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of first frequency shift signal series having a higher frequency than the fundamental sampling frequency, and a second circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of second frequency shift signal series having a lower frequency than the fundamental sampling frequency. The first and second circular shifters create each of the signal series by selecting a signal sample out of the input fundamental signal series according to a count value of a phase shift cumulative counter and a predetermined rule related to the frequency shift.

Abstract: A clock generation circuit for a digital video processing apparatus which has a simple structure and can be stably worked in both luminance and color signal systems. A color burst phase error signal indicative of phase difference of a color burst signal is produced on the basis of two color difference signals, a sampling clock signal is generated in accordance with the color burst phase error signal, the sampling clock is divided in order to produce a chrominance subcarrier signal, and the phase of the chrominance subcarrier signal is adjusted in accordance with the color burst phase error signal.