Abstract: An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Abstract: A medical instrument for use in combination with an endoscope having an operating shaft and a pair of tongs. The instrument has a drive mechanism provided between the operating shaft and the tongs, for opening and closing the tongs. The drive mechanism can apply an additional force to the tongs even after the tongs have closed completely.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Abstract: Disclosed is an assembly seal for use in assembly comprising: packing formed in a predetermined shape from an elastic material; a core within the packing for providing substantial rigidity such that can maintain the desired shape of the packing; and a base for supporting the core, the base having substantial rigidity and being connected to the core portion in such a manner that the base can be easily separated from the core by a cutting operation. The assembly seal is used in an assembly method for assembling a plurality of parts into a set of assembled parts incorporating packing. The assembly method comprises the steps of: positioning the assembly seal so that the packing of the assembly seal is positioned at a specified position on one part of a set of assembled parts; separating the base of the assembly seal from the packing; removing the base so that only the packing of the assembly seal is left on said one part; and fitting the other parts of said set of assembled parts to said one part.

Abstract: A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Abstract: A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Abstract: This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Abstract: A shift circuit 213 used in arithmetic operations is provided with the shift width generating circuit 217 which generates a shift width data from lower bits of an access address and an access size, and a circuit is provided to generated data comprising the first select output circuit 214, the third select output circuit 216 and the like which generate a data by merging byte by byte selected from either an output of the shift circuit 213 or a value of a register of a register file 210 according to the combination of the lower bits of the access address and the access size. It is possible to align the data in the shift circuit 213 which is provided for the purpose of arithmetic operations, and exclusive alignment circuit is made unnecessary thereby enabling it to reduce the amount of hardware.

Abstract: A cloth pick-up apparatus is used which comprises pressing mechanism for a pressing one end of the top cloth piece from the upper side, a catch roller having on a part of its circumferential surface catch needles and movable toward and away from the other end of the top cloth piece, the catch roller being adapted to be driven for rotation to feed the top cloth piece in a direction remote from the pressing mechanism, a feed roller rotatable in timed relation with the catch roller, and a pressure roller movable toward and away from a cloth-piece-feed surface of the feed roller and rotatable in cooperation with the feed roller. The catch roller is rotated touching one end of front face of the cloth pieces with the other end of the cloth piece pressed by the pressing roller so that the upper most cloth piece is caught by the catch needles and, at the same time, is raised.

Abstract: A data processor which is provided with a flag in a Processor Status Word (PSW) 116 for storing prohibiting/enabling status for receiving all of the interrupt requests, and in which the instruction execution control unit 114 controls so that the flag becomes in the enabling status when an interrupt request having a priority level is received and the flag becomes in the prohibiting status when an interrupt request having no priority level is received. Hence, for interrupt requests having priority levels, an interrupt request of high priority level can be received immediately without via the interrupt prohibiting status. For interrupt requests having priority levels, it becomes possible to receive an interrupt request of higher priority level without via the interrupt prohibiting status. For interrupt requests having no priority level such as for debugger and the like, it becomes unnecessary to perform a multi-interrupt processing.

Abstract: A data processor, comprises: a microaddress input selector 252 which, when decoding an instruction code, generates a main microaddress signal 212 corresponding to an operation code part, a submicroaddress signal 218 corresponding to an addressing mode designating part and an address calculation request signal 233 indicating whether address calculation is necessary or not, and selects an address signal corresponding to an operation code part or to an addressing mode designating part responsive to the address calculation request signal 233; and an instruction execution control unit control circuit 256 which controls the microaddress input selector 252; and is capable of executing the instruction having the addressing mode designating part independent from the operation code, rapidly and with a small microprogram size.

Abstract: A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test so that a plurality of instructions are executed in parallel with simple control.

Abstract: A screw-type resin injection apparatus for injection molding which includes a cylinder element having a cylinder chamber for receiving resin therein, and having, at an end portion, a nozzle for injecting the resin. A screw element is arranged within the cylinder chamber in a manner allowing rotation and axial movement. A rotary drive shaft is connected to the screw element telescopically so as to be capable of transmitting a torque. The rotary drive shaft is rotatively driven by a motor. A fluid pressure cylinder unit is arranged laterally of the cylinder element in parallel relation thereto. The fluid pressure cylinder unit is rotatably engaged with the screw element to drive the screw axially. Preferably, the screw element is provided with a mixing screw portion which has a screw groove small in pitch and large in lead angle and an axial groove extending axially.

Abstract: A data processing system which is provided with a plurality of operation units and a function which executes a plurality of instructions in parallel by each of these plurality of operation units, respectively, wherein operation results executed by these plurality of operation units are reflected on flags which are included in a processor status word (PSW), thereby, those plurality of instructions are executed in parallel in the respective different operation units, and at that time, results of operation processing of the respective instructions are reflected on the flags included in the PSW, then, the flags can be updated by simple control, and the operation results executed by those plurality of operation units are reflected on the flags included in the PSW according to the order of execution of the instructions, thereby, those plurality of instructions are executed in parallel by the respective different operation units, and at that time, the results of operation processing of the respective instructions ar

Abstract: A method and apparatus for processing exceptions in a microprocessor having a plurality of pipelined stages. The method comprises the steps of generating an exception processing code at a given stage to indicate the occurrence of an exception at the given stage; temporarily stopping processing at the given stage; transferring the exception processing code to a special stage; decoding said exception processing code at the special stage; and causing the pipeline to execute exception processing when the exception processing code is decoded at the special stage. Using the invention, the microprocessor can avoid much of the delay and complexity resulting from using an external circuit to control exception processing and can cope with the occurrence of an exception at any stage without prematurely cancelling or reexecuting processing steps. The invention is simplified in both hardware and software, and can easily cope with expansion of the number of stages.

Abstract: Cosmetic comprising (A) a specific acryl-silicone graft copolymer having an organosiloxane side chain is disclosed. The copolymer is prepared by radical polymerization of (i) a dimethylpolysiloxane compound having a polymerizable radical group on one of the molecular chain terminals and (ii) a radically polymerizable monomer comprising as major components an acrylate or methacrylate, or both. Various cosmetics including makeup cosmetics, o/w emulsion cosmetics, and w/o emulsion cosmetics, are prepared by using the copolymer in combination with (B) a low-viscosity silicone oil, (C) a partially cross-linked organopolysiloxane polymeric compound, (D) a low-boiling-point oil, (E) a volatile solvent, (F) a cosmetic powder material, (G) a polyacrylic acid, (H) a volatile hydrocarbon, (I) a surface active agent, or (J) water. The cosmetic compositions give a good sensation upon use, and exhibit superior water-repellency, water-resistance, oilresistance, and good retentiveness of the makeup.

Abstract: A data processor in accordance with the present invention can normally operate bit-string data while avoiding a breakage of the data even in the case where a read-out area of the bit string and a write-in area thereof are overlapped by each other by providing an operation code of an instruction with an option designating the direction of bit processing.

Abstract: Cosmetic comprising (A) a specific acryl-silicone graft copolymer having an organosiloxane side chain is disclosed. The copolymer is prepared by radical polymerization of (i) a dimethylpolysiloxane compound having a polymerizable radical group on one of the molecular chain terminals and (ii) a radically polymerizable monomer comprising as major components an acrylate or methacrylate, or both. Various cosmetics including makeup cosmetics, o/w emulsion cosmetics, and w/o emulsion cosmetics, are prepared by using the copolymer in combination with (B) a low-viscosity silicone oil, (C) a partially cross-linked organopolysiloxane polymeric compound, (D) a low-boiling-point oil, (E) a volatile solvent, (F) a cosmetic powder material, (G) a polyacrylic acid, (H) a volatile hydrocarbon, (I) a surface active agent, or (J) water. The cosmetic compositions give a good sensation upon use, and exhibit superior water-repellency, water-resistance, oil-resistance, and good retentiveness of the makeup.