Patents by Inventor Toru Shonai
Toru Shonai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7281249Abstract: A computer controls I/O allocation for partitions independently of CPU allocation and, in each I/O adapter and partition, the computer has a scheduling means controlling allocation for partitions of the I/O adapter by time sharing, a means to allocate the I/O adapter to partitions by space sharing and a means to dynamically change said allocation made by a partition-control program. Further, the computer has a means to monitor input/output performance of each partition, and a means to maintain SLA of a user program according to performance of each partition.Type: GrantFiled: August 30, 2001Date of Patent: October 9, 2007Assignee: Hitachi, Ltd.Inventors: Toshiaki Tarui, Shin Kameyama, Frederico Buchholz Maciel, Toru Shonai
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Patent number: 7206818Abstract: Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.Type: GrantFiled: August 4, 2003Date of Patent: April 17, 2007Assignee: Hitachi, Ltd.Inventors: Toshio Okochi, Toru Shonai, Naoki Hamanaka, Naohiko Irie, Hideya Akashi
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Patent number: 7062559Abstract: When a load of a user is fluctuated, a data center dynamically changes resource allocation to the user according to the load and holds security for each user. A control program on a data center managing server creates a VLAN configuration table so as to allocate a user-dedicated VLAN including plural network switches for each user company, thereby configuring the ports of a load balancer and network switches allocated to a user to the user-dedicated VLAN. A VPN is configured from the user to the data center, whereby a VLAN tagging technique is used to hold security of the user from the user to the data center. The control program compares a user condition setting table created along the service level agreement for each user with the monitoring result of the computer operating state (the CPU utilization history in a VLAN operation table) to dynamically change the computer allocation and VLAN configuration at unsatisfied agreement.Type: GrantFiled: February 25, 2002Date of Patent: June 13, 2006Assignee: Hitachi,Ltd.Inventors: Yutaka Yoshimura, Toshiaki Tarui, Frederico Buchholz Maciel, Toru Shonai
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Patent number: 6874053Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.Type: GrantFiled: September 5, 2003Date of Patent: March 29, 2005Assignee: Hitachi, Ltd.Inventors: Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara
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Publication number: 20040177143Abstract: To provide a method for managing data processing devices, in which the misidentification of a management target can be prevented. The method for managing data processing devices is applied to a system in which a plurality of container mechanisms are provided each of which contains a plurality of data processing devices and a management unit is provided which monitors each data processing device to collect information concerning the state of the data processing devices and orders management operations to be performed on the data processing devices based on the collected information, this method for managing data processing devices including: specifying a container mechanism containing a data processing device on which a management operation needs to be performed; and displaying information about the management operation on a specified container mechanism side.Type: ApplicationFiled: July 28, 2003Publication date: September 9, 2004Inventors: Frederico Buchholz Maciel, Shin Kameyama, Toru Shonai, Toshiaki Tarui, Mineyoshi Masuda
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Patent number: 6789173Abstract: In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.Type: GrantFiled: June 2, 2000Date of Patent: September 7, 2004Assignee: Hitachi, Ltd.Inventors: Tsuyoshi Tanaka, Hideya Akashi, Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai
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Publication number: 20040054855Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.Type: ApplicationFiled: September 5, 2003Publication date: March 18, 2004Applicant: Hitachi, Ltd.Inventors: Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara
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Publication number: 20040024839Abstract: Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.Type: ApplicationFiled: August 4, 2003Publication date: February 5, 2004Inventors: Toshio Okochi, Toru Shonai, Naoki Hamanaka, Naohiko Irie, Hideya Akashi
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Patent number: 6636926Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.Type: GrantFiled: December 21, 2000Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara
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Patent number: 6591325Abstract: An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs.Type: GrantFiled: April 11, 2000Date of Patent: July 8, 2003Assignee: Hitachi, Ltd.Inventors: Hideya Akashi, Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada, Masamori Kashiyama
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Publication number: 20030069972Abstract: When a load of a user is fluctuated, a data center dynamically changes resource allocation to the user according to the load and holds security for each user.Type: ApplicationFiled: February 25, 2002Publication date: April 10, 2003Inventors: Yutaka Yoshimura, Toshiaki Tarui, Frederico Buchholz Maciel, Toru Shonai
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Patent number: 6546471Abstract: A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is “0”, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers.Type: GrantFiled: February 18, 2000Date of Patent: April 8, 2003Assignee: Hitachi, Ltd.Inventors: Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi, Hideya Akashi
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Patent number: 6516391Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.Type: GrantFiled: March 13, 2000Date of Patent: February 4, 2003Assignee: Hitachi, Ltd.Inventors: Yuji Tsushima, Hideya Akashi, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada, Masamori Kashiyama
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Patent number: 6438653Abstract: A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.Type: GrantFiled: June 14, 1999Date of Patent: August 20, 2002Assignee: Hitachi, Ltd.Inventors: Hideya Akashi, Toshio Okochi, Toru Shonai, Masamori Kashiyama
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Publication number: 20020112102Abstract: A computer controls I/O allocation for partitions independently of CPU allocation and, in each I/O adapter and partition, the computer has a scheduling means controlling allocation for partitions of the I/O adapter by time sharing, a means to allocate the I/O adapter to partitions by space sharing and a means to dynamically change said allocation made by a partition-control program. Further, the computer has a means to monitor input/output performance of each partition, and a means to maintain SLA of a user program according to performance of each partition.Type: ApplicationFiled: August 30, 2001Publication date: August 15, 2002Applicant: Hitachi, Ltd.Inventors: Toshiaki Tarui, Shin Kameyama, Frederico Buchholz Maciel, Toru Shonai
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Publication number: 20020059427Abstract: A data center allocates computer resources independently to each user company, and automatically changes a computer allocation in real time in accordance with each load. A control program forms a computer allocation control table for each service level contract made between the data center and each user company, and sets the table to a load allocating apparatus. A table is formed which is used for searching a user company identifier from an IP address in a user request packet. The load allocating apparatus checks a service level contract from the user request packet and transfers the user request packet to a proper computer group. The control program compares the service level contract with the monitoring result of the operation state of computers, and if the contract condition is not satisfied, the number of allocated computers is changed.Type: ApplicationFiled: July 5, 2001Publication date: May 16, 2002Applicant: Hitachi, Ltd.Inventors: Yoshiko Tamaki, Toru Shonai, Nobutoshi Sagawa, Shun Kawabe
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Patent number: 6389518Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.Type: GrantFiled: March 13, 2000Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Yuji Tsushima, Hideya Akashi, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada, Masamori Kashiyama
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Publication number: 20010005873Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.Type: ApplicationFiled: December 21, 2000Publication date: June 28, 2001Applicant: Hitachi, Ltd.Inventors: Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara
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Patent number: 6088770Abstract: A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers.Type: GrantFiled: February 26, 1998Date of Patent: July 11, 2000Assignee: Hitachi, Ltd.Inventors: Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi, Hideya Akashi
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Patent number: 5504690Abstract: An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed.Type: GrantFiled: August 16, 1993Date of Patent: April 2, 1996Assignee: Hitachi, Ltd.Inventors: Naohiro Kageyama, Toru Shonai, Rikako Suzuki, Takashi Okada, Kazuhiko Iijima, Hiroyuki Nakajima, Chihei Miura, Tsuguo Shimizu