Patents by Inventor Toru SHONO

Toru SHONO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE
    Publication number: 20220085192
    Abstract: A semiconductor part includes a terminal, a first region, and a second region positioned between the first region and the terminal. A ratio of a surface area of a fourth semiconductor layer to a surface area of a third semiconductor layer in the second region is greater than a ratio of a surface area of the fourth semiconductor layer to a surface area of the third semiconductor layer in the first region.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 17, 2022
    Inventors: Akihiro TANAKA, Tetsuhiro SAISHO, Toru SHONO, Koji ONISHI
  • Semiconductor device and control system
    Patent number: 11171216
    Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a first switching element, a second switching element, and a conductor. The conductor is provided at least in part on the first semiconductor layer and located between the first switching element and the second switching element in a first direction.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidetoshi Asahara, Akihiro Tanaka, Toru Shono
  • SEMICONDUCTOR DEVICE AND CONTROL SYSTEM
    Publication number: 20190088749
    Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a first switching element, a second switching element, and a conductor. The conductor is provided at least in part on the first semiconductor layer and located between the first switching element and the second switching element in a first direction.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidetoshi ASAHARA, Akihiro TANAKA, Toru SHONO
  • Semiconductor device
    Patent number: 9601481
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the semiconductor device includes a second semiconductor layer of the second dopant type on the first semiconductor layer, a third semiconductor layer of the first dopant type on the second semiconductor layer, and a second electrode extending though the second and third semiconductor layers and inwardly of the first semiconductor layer. A second region of the semiconductor device includes an insulating layer over the first semiconductor layer, a fourth semiconductor layer of the first or second dopant type on the insulating layer, a fifth semiconductor layer of a different dopant type on the insulating layer and surrounding the fourth semiconductor layer, and a sixth semiconductor layer of the same dopant type on the insulation layer and surrounding the fifth semiconductor layer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Shono
  • SEMICONDUCTOR DEVICE
    Publication number: 20160079232
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the semiconductor device includes a second semiconductor layer of the second dopant type on the first semiconductor layer, a third semiconductor layer of the first dopant type on the second semiconductor layer, and a second electrode extending though the second and third semiconductor layers and inwardly of the first semiconductor layer. A second region of the semiconductor device includes an insulating layer over the first semiconductor layer, a fourth semiconductor layer of the first or second dopant type on the insulating layer, a fifth semiconductor layer of a different dopant type on the insulating layer and surrounding the fourth semiconductor layer, and a sixth semiconductor layer of the same dopant type on the insulation layer and surrounding the fifth semiconductor layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventor: Toru SHONO