Patents by Inventor Toru Suga

Toru Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11925458
    Abstract: A motion state monitoring system, a training support system, a motion state monitoring method, and a program capable of suitably managing measurement results according to an attaching direction of a sensor are provided. A motion state monitoring system according to the present disclosure monitors a motion state of a target part of a subject's body. The motion state monitoring system includes an acquisition unit, an attaching direction detection unit, and a control processing unit. The acquisition unit acquires sensing information of a sensor attached to the target part. The attaching direction detection unit detects an attaching direction of the sensor. The control processing unit outputs information related to the sensing information in association with the attaching direction.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: March 12, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Makoto Kobayashi, Toru Miyagawa, Issei Nakashima, Keisuke Suga, Masayuki Imaida, Manabu Yamamoto, Yohei Otaka, Masaki Katoh, Asuka Hirano, Taiki Yoshida
  • Patent number: 5717232
    Abstract: A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are .epsilon.(1) and .epsilon.(2) respectively .epsilon.(1)<.epsilon.(2) and the water absorption ratio of the first dielectric layer is greater than the water absorption ratio of the second dielectric layer.
    Type: Grant
    Filed: April 16, 1996
    Date of Patent: February 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Inoue, Souichi Imamura, Masanori Ochi, Shigehiro Hosoi, Toru Suga, Takashi Kimura
  • Patent number: 5229637
    Abstract: In a semiconductor device constituting a GaAs MESFET, a GaAs substrate is prepared from a base material containing boron ions as a dopant impurity having a total impurity concentration of 2.times.10.sup.17 atoms/cm.sup.3 or more. The boron ions are introduced into the GaAs substrate during crystal growth so that a uniform distribution of boron ions in the substrate results. Electrode layers are formed at predetermined portions on the GaAs substrate, and an active layer is formed to be adjacent to the electrode layers by ion implantation. Source and drain electrodes are formed on the electrode layers respectively, and a gate electrode is formed on the active layer.
    Type: Grant
    Filed: July 15, 1992
    Date of Patent: July 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Suga, Kazuhiko Inoue
  • Patent number: 5204278
    Abstract: After a silicon nitride film is deposited on a compound semiconductor substrate, another insulating film such as a silicon dioxide film is provided thereon so as to define a channel region in the semiconductor substrate. Impurity ions such as Si ions are selectively implanted into the semiconductor substrate in the presence of the silicon nitride film and the insulating film, thereby providing source and drain regions and the channel region therein. The insulating film and the silicon nitride film located above the channel region are successively removed to provide a Schottky gate electrode thereon. The silicon nitride film is selectively removed from the substrate surface to provide source and drain electrodes on their regions. Accordingly, MESFETs can be produced without exposing the substrate surface during its manufacture.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Imamura, Toru Suga
  • Patent number: 5153703
    Abstract: In a semiconductor device constituting a GaAs MESFET, a GaAs substrate is prepared from a base material containing boron and carbon ions as impurities having a total impurity concentration of 2.times.10.sup.17 atoms/cm.sup.3 or more. Electrode layers are formed at predetermined portions on the GaAs substrate, and an active layer is formed to be adjacent to the electrode layers by ion implantation. Source and drain electrodes are formed on the electrode layers, respectively, and a gate electrode is formed on the active layer.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: October 6, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Suga, Kazuhiko Inoue
  • Patent number: 4972241
    Abstract: A chip including a Hall element for detecting a magnetic force is p repared. On the chip is formed an unhardened magnetic resin layer, which is formed of a mixture of soft magnetic powder an dsilicone rubber. The unhardened magnetic resin layer is applied with a magnetic field and is stretched in a direction perpendicular to one face of the chip, so that its top portion is formed in a substantially conical shape and its bottom portion is formed in a substantially rectangular block, the ratio of the length Wa of its base to its height Wb, Wb/Wa, being equal to or greater than 1. The magnetic resin layer is then hardened. As a result, a magnetic force detecting semiconductor device is provided, which has a magnetic resin layer with a high magnetic force convergence that has its top portion formed in a conical shape and its bottom portion formed in a rectangular block, the ratio of the length of its base to its height being equal to and greater than 1.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: November 20, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikazu Fukuda, Toru Suga, Yutaka Tomisawa
  • Patent number: 4947236
    Abstract: A semiconductor device includes an SIL type package for projection of the pellet of a Hall sensor used for detecting the position of a motor. An inclined portion is formed on an edge portion which faces the motor coil so that the edge portion will come into area-contact with the motor coil even if they come into contact with each other, thus causing no stress concentration on the motor coil.
    Type: Grant
    Filed: December 1, 1988
    Date of Patent: August 7, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Suga, Kazuhiko Inoue
  • Patent number: 4868920
    Abstract: A MESFET device includes a semi-insulative substrate, a source region, a drain region, a channel region, a source electrode, a drain electrode, a gate electrode, and a gate-electrode pad. The source region, drain region, and the channel region are formed in a surface region of the substrate. The three electrode and the gate-electrode pad are formed on the substrate. The MESFET device further comprises a conductive layer formed on the substrate and surrounds the source electrode and the gate-electrode pad. The conductive layer is connected to the drain electrode.
    Type: Grant
    Filed: March 24, 1988
    Date of Patent: September 19, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Inoue, Toru Suga