Patents by Inventor Toru Taura

Toru Taura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090233546
    Abstract: An interface circuit, which uses electromagnetic induction to perform a signal transmission, comprises a transmission coil and a transmission circuit that provides a signal to the transmission coil, thereby causing the transmission coil to output a triangular or roughly triangular magnetic field signal.
    Type: Application
    Filed: August 4, 2006
    Publication date: September 17, 2009
    Applicant: NEC CORPORATION
    Inventors: Hideki Sasaki, Muneo Fukaishi, Toru Taura
  • Publication number: 20090135573
    Abstract: A circuit board device includes: plurality of wiring boards (101 and 102) in which terminals are provided on the front and back surfaces and vias are provided for connecting the terminals together, an anisotropic conductive member (103) arranged between wiring boards (101 and 102) for connecting the electrodes of one wiring board to the electrodes of another wiring board, a functional block (104) composed of a metal material and arranged between the wiring boards (101 and 102) to enclose anisotropic conductive member (103), and a pair of holding blocks (105 and 106) composed of a metal material arranged to clamp the plurality of wiring boards (101 and 102), wherein the plurality of wiring boards (101 and 102), while in a state of being clamped between the pair of holding blocks (105 and 106), is connected together by the anisotropic conductive member (103) and the terminals provided on each of the wiring boards (101 and 102), the functional block (104), and the holding blocks (105 and 106) are electrically co
    Type: Application
    Filed: May 14, 2007
    Publication date: May 28, 2009
    Inventors: Junya Sato, Toru Taura, Nobuhiro Mikami, Shinji Watanabe, Atsumasa Sawada, Nozomu Nishimura
  • Publication number: 20080265933
    Abstract: The semiconductor device testing apparatus according to the present invention has a testing LSI; a power supply unit; and an intermediate substrate provided so that there is a connection between the testing LSI, and the power supply unit and tester. The testing LSI has a testing circuit and a waveform shaping circuit; a dielectric material layer disposed so as to face a tested semiconductor device; an electrode disposed in a position that corresponds to a position of an external terminal electrode of the tested semiconductor device on a surface of the dielectric material layer facing the tested semiconductor device; and a first penetrating electrode that passes completely through the dielectric material layer, is connected to the electrode, and is used for exchanging signals with the exterior.
    Type: Application
    Filed: July 19, 2006
    Publication date: October 30, 2008
    Applicant: NEC CORPORATION
    Inventors: Michinobu Tanioka, Shigeki Hoshino, Toru Taura
  • Patent number: 6486688
    Abstract: A semiconductor device testing apparatus that has a laminate structure composed of a contact sheet having a first opening, an elastic sheet having a second opening and a base plate having a third opening. A supply voltage is applied to an external terminal located on a peripheral portion of the contact sheet. A probe of a probe portion is contacted to a signal electrode of a semiconductor device through the third, second and first openings.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 26, 2002
    Assignee: NEC Corporation
    Inventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
  • Patent number: 6400168
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: June 4, 2002
    Assignees: NEC Corporation, Anritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
  • Publication number: 20020036514
    Abstract: There is provided a semiconductor device testing apparatus that can perform a measurement of an electrical characteristic of a semiconductor device that has many electrodes and operates at high frequency. The semiconductor device testing apparatus comprises: a contact sheet (105) having supply voltage electrodes (107c, 107b) of bump structure on a thin insulator sheet (105a), which contact with a source electrode (100c) and a ground electrode (100b) of a semiconductor device (100), and a first opening (113) located at a position facing a signal (100a) of the semiconductor device (100).
    Type: Application
    Filed: September 20, 2001
    Publication date: March 28, 2002
    Applicant: NEC CORPORATION
    Inventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
  • Publication number: 20010038294
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Application
    Filed: June 22, 2001
    Publication date: November 8, 2001
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
  • Patent number: 6310483
    Abstract: A high-frequency probe according to the present invention comprises a probe chip that has an end part that is pressed to an electrode and is covered by a electrically conductive outer enclosure, and slides in a vertical direction by an inner surface of this electrically conductive outer enclosure inside this electrically conductive outer enclosure. A signal conductive pattern is fixed inside this probe chip and is connected with a inner conductor having elasticity. The inner conductor can be bent in the vertical direction at a central part of a hole having an opening, which is sufficiently long in the vertical direction, in the center space of a ground conductor, which is fixed to an end part of the main block, when the inner conductor is pressed due to contact of the end part. In addition, the high-frequency probe has a thin shape of a maximum thickness in a transverse direction which is perpendicular to the vertical direction that is a direction of the probe being pressed to a device electrode.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: October 30, 2001
    Assignees: NEC Corporation, Anritsu Corporation
    Inventors: Toru Taura, Hirobumi Inoue, Masao Tanehashi, Kouji Matsunaga, Yuuichi Yamagishi, Satoshi Hayakawa, Hironori Tsugane
  • Patent number: 6281691
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block . A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: August 28, 2001
    Assignees: NEC Corporation, Amritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
  • Patent number: 6242930
    Abstract: In a high-frequency probe having a detachable end according to the present invention, parts relating to replacement of an end unit are three parts, that is, an end unit, a probe body, and a pressure block. The end unit comprises a coaxial cable, two slender plate-like ground plates. The coaxial cable is linear in the direction of the end of the high-frequency probe. The ground plates sandwich the coaxial cable. The probe body has an end unit support surface, a circuit board, an end unit arrangement surface and an end part guide. The end unit support surface forms a perpendicular surface used for fixing the end unit to a predetermined position in the end side of the central block in a central part of a surface of the body block. The circuit board connects the end unit to a coaxial connector. The end unit arrangement surface forms a plane in an end side of the body block. And further the guide groove positions and fixes the ground plate in the end part.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: June 5, 2001
    Assignees: NEC Corporation, Antritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa, Hironori Tsugane
  • Patent number: 6229321
    Abstract: A process for manufacturing a high frequency multichip module includes a reception inspection step which includes steps of preparing a vertical-type probe, setting the high frequency bare chip on a device stage, and measuring high frequency characteristics of the high frequency bare chip using the vertical-type probe. The prepared vertical-type probe has a center conductor and ground conductors arranged at both sides of the tip portion of the center conductor in the vertical direction in which the probe is pressed to electrodes of the high frequency bare chip. The high frequency bare chip has a ground electrode disposed at the opposite side of the chip from the signal electrodes on the upper surface of a device stage. Then, only a good product is fed to the next step. After the reception inspection, the process goes to a component mounting step.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: May 8, 2001
    Assignees: NEC Corporation, Anritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Masahiko Nikaidou, Toru Taura, Yuuichi Yamagishi, Satoshi Hayakawa
  • Patent number: 5614944
    Abstract: In a video signal test, a sync signal test is first performed in which specification items of sync signals are measured. If the result is good, then a dot level test is performed using a dot discriminating pattern in which a dot level of the video signal changes between the maximum value and the minimum value for every dot. If the result is good, then a gradation test is finally performed using a gradation change pattern in which the gradation gradually changes for every horizontal line. In a case that the gradation test result is determined to be good, the functions of the video signal generator are finally judged to be good. On the other hand, if any one of the testing results is not good, the function test is ended at that stage without executing the next test.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: March 25, 1997
    Assignee: NEC Corporation
    Inventors: Toru Taura, Hirobumi Inoue