Patents by Inventor Toru Ueguri

Toru Ueguri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9704844
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 11, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Publication number: 20160233204
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the leadframe, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Katsuhiko FUNATSU, Tomoaki UNO, Toru UEGURI, Yukihiro SATO
  • Patent number: 9343451
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 17, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Publication number: 20150228559
    Abstract: To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.
    Type: Application
    Filed: April 26, 2015
    Publication date: August 13, 2015
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yasushi Takahashi
  • Publication number: 20150214209
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Application
    Filed: April 13, 2015
    Publication date: July 30, 2015
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Patent number: 9029197
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Patent number: 9029995
    Abstract: To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yasushi Takahashi
  • Publication number: 20140084436
    Abstract: To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yasushi Takahashi
  • Publication number: 20140087520
    Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato
  • Patent number: 8253247
    Abstract: In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: August 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriko Numata, Hiroshi Sato, Toru Ueguri
  • Publication number: 20110073921
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Inventors: Hideaki TAMIMOTO, Takumi SOBA, Toru UEGURI, Kazuo KUDO
  • Patent number: 7863107
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Tamimoto, Takumi Soba, Toru Ueguri, Kazuo Kudo
  • Publication number: 20100258945
    Abstract: In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses 10a are formed beforehand at both end portions respectively of the wedge tool lest both end portions in the width direction of the Al ribbon bonded to the pad should contact the pressure bonding surface of the wedge tool.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 14, 2010
    Inventors: NORIKO NUMATA, Hiroshi Sato, Toru Ueguri
  • Publication number: 20090152697
    Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Inventors: Hideaki Tamimoto, Takumi Soba, Toru Ueguri, Kazuo Kudo