Abstract: According to one embodiment, a database management method manages a plurality of clusters each having a representative vector. When registering a first D-dimensional vector in a vector database, the method identifies a cluster that has a representative vector closest to the first D-dimensional vector among the plurality of clusters, and calculates D differences obtained by subtracting D elements contained in the representative vector of the identified cluster from D elements contained in the first D-dimensional vector, respectively. The method stores an identifier of the identified cluster and the D differences in the vector database, as position information of the first D-dimensional vector.

Abstract: According to one embodiment, an approximate nearest neighbor search method for a vector database in which N D-dimensional vectors are stored, includes managing N pieces of first direction information acquired in advance. The N pieces of first direction information each represent a direction from a first reference vector of D dimensions to each of the N D-dimensional vectors. The method includes receiving a query vector of D dimensions, calculating second direction information representing a direction from the first reference vector to the query vector, and searching for an approximate nearest neighbor vector of the query vector from the N D-dimensional vectors by using the N pieces of first direction information and the second direction information.

Abstract: According to one embodiment, an approximate nearest neighbor search method manages graph-based index information for defining an inter-cluster graph. The approximate nearest neighbor search method searches for a vector closest to a query vector from vectors belonging to a search start cluster that is closest to the query vector among a plurality of clusters. The approximate nearest neighbor search method selects one or more search target clusters close to the search start cluster while traversing the inter-cluster graph, and searches for a vector closest to the query vector from vectors belonging to each of the one or more search target clusters.

Abstract: According to one embodiment, a processor of a cache server delivers content acquired from an origin server to a client, using a storage device as a cache of the contents. When an error occurs in reading the content from the storage device, the processor determines whether or not to recover the content based on a recovery amount of a delivery capability of the cache server as a result of recovering the content and a cost of writing data to the storage device associated with recovery of the content. When determined to recover the content, the processor selects a content recovery method based on a first remaining retention period during which the content should be retained and a second remaining retention period until the content is to be erased from the storage device.

Abstract: A first vector database stored in a storage device includes a group of first information pieces each indicating one of a plurality of first vectors that correspond to a plurality of nodes of a first directed graph. A management method is capable of reducing the amount of data written in the storage device during updates. The method includes, while generating a second directed graph that includes two or more nodes corresponding to two or more second vectors, generating, in a volatile memory, a second vector database in which a group of third information pieces each indicating one of the two or more second vectors, is recorded. The method further includes combining the first directed graph with the second directed graph by updating one information piece of the group of first information pieces and the group of third information pieces, and storing the second vector database in the storage device.

Abstract: According to one embodiment, a processor of a cache server delivers content acquired from an origin server to a client, using a storage device as a cache of the contents. When an error occurs in reading the content from the storage device, the processor determines whether or not to recover the content based on a recovery amount of a delivery capability of the cache server as a result of recovering the content and a cost of writing data to the storage device associated with recovery of the content. When determined to recover the content, the processor selects a content recovery method based on a first remaining retention period during which the content should be retained and a second remaining retention period until the content is to be erased from the storage device.

Abstract: A memory access method is employed in a multiprocessor system which includes a plurality of system modules coupled via a crossbar module, where each of the system modules includes a buffer which holds data and a plurality of processors having a cache memory which temporarily holds data. The memory access method includes a step, responsive to a read request from a processor within an arbitrary system module, holding data preread from a system module other than the arbitrary system module in a buffer within the crossbar module.

Abstract: A multiprocessor system includes a plurality of system modules each having a plurality of processors, a transfer controller and a first crossbar, a crossbar module including a second crossbar, a control bus coupling the transfer controller of each of the system modules to the crossbar module, and a data bus coupling the first crossbar of each of the system modules to the crossbar module. Within an arbitrary one of the system modules, the first crossbar outputs a data packet to the data bus in response to a command signal from the transfer controller after the transfer controller outputs a control information packet to the control bus.

Abstract: An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend or restrain issuance of address transactions, other than the excessively retried address transaction, and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of a presence of the excessively retried address transaction by the bus-control unit.

Abstract: A multiprocessor system provided with a plurality of ports (54-1 to 54-n+m) forming processors or bus bridge units, is constructed to include a system controller (51, 51A) coupling the plurality of ports via address buses and control signal lines, a data bus controller (52) coupling the plurality of ports via data buses, and a conversion unit (58, 58A) converting at least one of commands, data and control signals at an intermediate part of a transfer path which is formed by at least one of the address buses, the data buses and the control signal lines.

Abstract: A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Abstract: A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.