Patents by Inventor Toruo TAKAGIWA

Toruo TAKAGIWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110032760
    Abstract: According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an Nth one of the shifts. N is an integer not less than 0).
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Inventor: Toruo TAKAGIWA