Abstract: Provided is a differential signal transmission apparatus that transmits a differential signal expressed by a potential difference between a positive signal and a negative signal, including a positive signal transmission line that transmits the positive signal; a negative signal transmission line that transmits the negative signal; and a delay compensating circuit that compensates for a time difference between the positive signal and the negative signal with a variable compensation time.

Abstract: Provided is a driver circuit that outputs a transmission signal according to a reception signal received from outside, including a first driver that outputs a voltage according to an input first signal; a second driver that receives the voltage output by the first driver as a power supply voltage and outputs the transmission signal according to the power supply voltage and an input second signal; and a control section that delays both the first signal and the second signal, according to a change of the reception signal, and causes the transmission signal according to the reception signal to be output from the second driver.

Abstract: Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that receives an output signal of the device under test, and makes judgment concerning pass/fail of the device under test based on the output signal; an internal circuit that exchanges signals between the device under test and the pattern generating section or the judging section; a first transmission line that connects the internal circuit to the device under test; and a first switch that connects the first transmission line to a ground potential in not testing the device under test, and cuts off the first transmission line from the ground potential in testing of the device under test.

Abstract: Provided is a driver circuit that has a first operational mode and a second operational mode and outputs an output signal according to an input signal. The driver circuit includes a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, is controlled to be disabled; a high precision driver section that, in the first operational mode, is controlled to be disabled and, in the second operational mode, outputs a source power having a predetermined voltage; and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, receives the source power from the high precision driver section, generates the output signal according to the input signal, and outputs the thus generated signal to the outside.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: Provided is a differential signal transmission apparatus that transmits a differential signal expressed by a potential difference between a positive signal and a negative signal, including a positive signal transmission line that transmits the positive signal; a negative signal transmission line that transmits the negative signal; and a delay compensating circuit that compensates for a time difference between the positive signal and the negative signal with a variable compensation time.

Abstract: Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside.

Abstract: Provided is a driver circuit that outputs a transmission signal according to a reception signal received from outside, including a first driver that outputs a voltage according to an input first signal; a second driver that receives the voltage output by the first driver as a power supply voltage and outputs the transmission signal according to the power supply voltage and an input second signal; and a control section that delays both the first signal and the second signal, according to a change of the reception signal, and causes the transmission signal according to the reception signal to be output from the second driver.

Abstract: There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first adjusting section that adjusts a phase difference between the input data signal and the input clock signal so as to be equal to a first phase difference, and outputs the resulting signals as a first data signal and a first clock signal, a phase varying section that outputs a second clock signal having a designated phase difference with respect to the first clock signal, and a second adjusting section that adjusts the phase difference of the second clock signal with respect to the first clock signal so as to be equal to a second phase difference, based on a result of obtaining the first clock signal at a varying timing of the second clock signal.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that receives an output signal of the device under test, and makes judgment concerning pass/fail of the device under test based on the output signal; an internal circuit that exchanges signals between the device under test and the pattern generating section or the judging section; a first transmission line that connects the internal circuit to the device under test; and a first switch that connects the first transmission line to a ground potential in not testing the device under test, and cuts off the first transmission line from the ground potential in testing of the device under test.

Abstract: A test apparatus for testing a device under test is provided. The test apparatus includes a test signal generating section for generating a test signal to be provided to the device under test, a driver circuit for providing the test signal to the device under test and a determination section for determining whether is good or bad of the device under test based on the output signal outputted by the device under test according to the test signal. The driver circuit includes a main driver and a sub-driver for outputting drive signals according to the test signal, respectively, a differentiating circuit for outputting a differentiated signal obtained by differentiating the drive signal outputted by the sub-driver and an adding section for providing a signal having the waveform according to the test signal which is obtained by adding the differentiated signal to the drive signal outputted by the main driver to the device under test.

Abstract: Provided is a driver circuit that has a first operational mode and a second operational mode and outputs an output signal according to an input signal. The driver circuit includes a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, is controlled to be disabled; a high precision driver section that, in the first operational mode, is controlled to be disabled and, in the second operational mode, outputs a source power having a predetermined voltage; and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, receives the source power from the high precision driver section, generates the output signal according to the input signal, and outputs the thus generated signal to the outside.

Abstract: Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: The present invention provides a terminator circuit including a potential variation detecting section that detects a variation in a potential at an end point to which an input signal is supplied, and a first current generating section that reduces an overshoot at the end point which is caused by the application of the input signal, by pulling a current from the end point, when the potential variation detecting section detects a rise in the potential at the end point. Here, the potential variation detecting section includes a comparison potential generating section that generates a comparison potential based on a reference potential, and a potential comparing section that compares the comparison potential which has risen in accordance with the rise in the potential at the end point, with the reference potential, and outputs a result of the comparison.

Abstract: A testing apparatus for testing a device under test is provided, wherein the testing apparatus includes: a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage; a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage and outputting to the device under test; a comparator setting unit for determining the first reference voltage so as to compensate for a delay amount of a reception signal received from the device under test and setting the comparator to be the first reference voltage; and a driver setting unit for determining the second reference voltage on the basis of the reference voltage of the comparator and setting the driver to be the second reference voltage.

Abstract: There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the delayed test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.

Abstract: There is provided a test apparatus that decides the good or bad of an electronic device adopting source synchronous clocking with high precision.

Abstract: There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first adjusting section that adjusts a phase difference between the input data signal and the input clock signal so as to be equal to a first phase difference, and outputs the resulting signals as a first data signal and a first clock signal, a phase varying section that outputs a second clock signal having a designated phase difference with respect to the first clock signal, and a second adjusting section that adjusts the phase difference of the second clock signal with respect to the first clock signal so as to be equal to a second phase difference, based on a result of obtaining the first clock signal at a varying timing of the second clock signal.