Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells are disposed in a matrix, each memory cell being connectable to any one of a plurality of bit lines, and a capacitance that suppresses coupling noise among the plurality of bit lines, the capacitance being added to at least one of the plurality of bit lines.

Abstract: According to one embodiment, a semiconductor integrated circuit device includes a first line to which a voltage is applied; a first circuit operating based on a data; a second circuit capable of retaining the data; a third circuit between the first line and the first circuit and capable of shutting off a supply of the voltage to the first circuit; and a fourth circuit including a resistor element, the resistor element connected between the first line and the second circuit. The fourth circuit supplies the voltage to the second circuit via the resistor element in a period in which the third circuit shut off the supply of the voltage to the first circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells are disposed in a matrix, each memory cell being connectable to any one of a plurality of bit lines, and a capacitance that suppresses coupling noise among the plurality of bit lines, the capacitance being added to at least one of the plurality of bit lines.

Abstract: A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

Abstract: A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units.

Abstract: A photo-mask that includes a first light shielding region which is narrow and elongated, and a second light shielding region which is wider and more elongated than the first light shielding region and is away from the first light shielding region. A phase shifter part and a non-phase shifter part are provided adjacently to both sides of the first light shielding region. Two phase shifter parts or two non-phase shifter parts are respectively provided adjacently to both sides of the second light shielding part.

Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.

Abstract: A photo-mask, a multiphase exposure method and a method of manufacturing a semiconductor device are disclosed. The photo-mask mask includes a first light shielding region which is narrow and elongated, and a second light shielding region which is wider and more elongated than the first light shielding region and is away from the first light shielding region. A phase shifter part and a non-phase shifter part are provided adjacently to both sides of the first light shielding region. Two phase shifter parts or two non-phase shifter parts are respectively provided adjacently to both sides of the second light shielding part.

Abstract: A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.