Patents by Inventor Toshiaki FUKUZUMI

Toshiaki FUKUZUMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170475
    Abstract: A method for manufacturing a semiconductor device includes providing a first integrated circuit element including a first semiconductor substrate and a first wiring layer, providing a second integrated circuit element including a second semiconductor substrate and a second wiring layer, bonding the first insulating layer and the second insulating layer to each other, and bonding the first electrode and the second electrode to each other. The first insulating layer contains an inorganic insulating material. A plurality of first openings recessed toward the first semiconductor substrate from a bonding surface bonded to the second insulating layer are provided at positions in the first insulating layer in the first wiring layer different from an arrangement position of the first electrode, and the plurality of first openings discontinuously surround the first electrode.
    Type: Application
    Filed: March 23, 2022
    Publication date: May 23, 2024
    Inventors: Shizu FUKUZUMI, Tomoaki SHIBATA, Toshiaki SHIRASAKA
  • Publication number: 20240170447
    Abstract: A method for manufacturing a semiconductor device includes providing a first integrated circuit element including a first semiconductor substrate, a first insulating film, and a first electrode, providing a second integrated circuit element including a second semiconductor substrate, a second insulating film, and a second electrode, bonding the first insulating film and the second insulating film to each other, and bonding the first electrode and the second electrode to each other. The first insulating film includes a first inorganic insulating layer and a first organic insulating layer. The second insulating film includes a second inorganic insulating layer and a second organic insulating layer. The thickness of the first organic insulating layer is smaller than the thickness of the first inorganic insulating layer, and the thickness of the second organic insulating layer is smaller than the thickness of the second inorganic insulating layer.
    Type: Application
    Filed: March 24, 2022
    Publication date: May 23, 2024
    Inventors: Tomoaki SHIBATA, Shizu FUKUZUMI, Toshiaki SHIRASAKA
  • Patent number: 10475809
    Abstract: A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Ito, Toshiaki Fukuzumi
  • Publication number: 20180130820
    Abstract: A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.
    Type: Application
    Filed: August 31, 2017
    Publication date: May 10, 2018
    Inventors: Takamasa ITO, Toshiaki FUKUZUMI