Abstract: An electrode structure includes: a plurality of pixel electrodes arranged separately from each other; and a plurality of dielectric layers laminated in a first direction with respect to the plurality of pixel electrodes, in which the plurality of dielectric layers includes: a first dielectric layer that spreads over the plurality of pixel electrodes in a direction intersecting with the first direction; and a second dielectric layer that includes dielectric material having a refractive index higher than that of the first dielectric layer, sandwiches the first dielectric layer together with the plurality of pixel electrodes, and has a slit at a position overlapping space between pixel electrodes adjacent when viewed from the first direction.

Abstract: An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween.

Abstract: An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween.

Abstract: A Darlington transistor having improved comprehensive electric characteristic and a bipolar transistor having improved high voltage characteristic are obtained. A collector resistivity .rho.N.sup.- (F) of a collector high resistivity layer (11) in a front stage side transistor chip (TF) is set to 80 5/8cm and its collector film thickness tN.sup.- (F) is set to 120 .mu.m, and a collector resistivity .rho.N.sup.- (R) of a collector high resistivity layer (13) in a rear stage side transistor chip (TR) is set to 45 .OMEGA.cm and its collector film thickness tN.sup.- (R) is set to 160 .mu.m. Since .rho.N.sup.- (F)>.rho.N.sup.- (R) and tN.sup.- (F)<tN.sup.- (R) are satisfied, a Darlington transistor having a good comprehensive electric characteristic can be obtained, and also, since .rho.N.sup.- (R)/tN.sup.- (R)<0.6 is satisfied, a bipolar transistor having a good high voltage characteristic can be obtained (FIG. 8).