Abstract: A low-cost digital image processing device constructed by using a simplified circuit is provided which is capable of reducing an amount of data of an image to be stored in a frame memory and of being applied to a display panel with a desired level of a resolution. In the digital image processing device, a video input signal is processed in a signal processing unit and is stored in a frame memory as image data. The frame memory is installed to play a role as, for example, a double buffer to smooth out transfer speed discrepancies between a video input signal and a video output signal. Dummy data is embedded in an image data read from the frame memory by a redundant pixel embedding section and the image data is fed to a display panel as a video output signal.

Abstract: A low-cost digital image processing device constructed by using a simplified circuit is provided which is capable of reducing an amount of data of an image to be stored in a frame memory and of being applied to a display panel with a desired level of a resolution. In the digital image processing device, a video input signal is processed in a signal processing unit and is stored in a frame memory as image data. The frame memory is installed to play a role as, for example, a double buffer to smooth out transfer speed discrepancies between a video input signal and a video output signal. Dummy data is embedded in an image data read from the frame memory by a redundant pixel embedding section and the image data is fed to a display panel as a video output signal.

Abstract: A method for accessing a frame memory integrated within a display panel driver driving a display panel is composed of serially performing write operations for writing sub-field data of a pixel line within the display panel for a plurality of sub-fields into the frame memory, and serially performing read operations for reading sub-field data of a plurality of pixel lines for a sub-field from the frame memory. At least two of the write operations are allowed to be performed between adjacent two of the read operations.

Abstract: In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with “0”. A Booth decoder divides the multiplier into a plurality of partial bit rows. A plurality of partial product generating circuits, each of which is arranged corresponding to corresponding one of the partial bit rows divided by the Booth decoder, each generates a partial product of a multiplicand and each corresponding one of the partial bit rows. In the case of performing the multiplication operation with low accuracy, the partial product generating circuits generating the partial products corresponding to the partial bit row of the least significant half the bits, generate partial products of each corresponding bit row and the least significant half the bits of the multiplicand, and generate partial products of each corresponding bit row and the most significant half the bits of the multiplicand.

Abstract: A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 &OHgr;.

Abstract: A semiconductor device provided with a field effect transistor having a electrode pads for wire-bonding comprises a first electrode pad for wire-bonding directly connected with the field effect transistor, and a second electrode pad for wire-bonding connected with the field effect transistor via a resistor. According to the semiconductor device, a chip used in the field effect transistor can be used in different frequencies by changing bonding.

Abstract: A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10&OHgr;.

Abstract: A semiconductor device has a plurality of transistor units each of which is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes. The gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 &OHgr;.

Abstract: An A/F ratio detecting arrangement includes a sensor casing having an oxygen sensor part arranged between first and second electrodes and an oxygen pump part arranged between third and fourth electrodes, which are heated by a heater. A signal output processing circuit serves to provide an A/F ratio signal. A signal switcher serves to provide a provisional oxygen content signal derived from the first and second electrodes when the oxygen pump part is not activated yet, and the A/F ratio signal when the oxygen pump part is activated.

Abstract: To obtain a clear-cut picture image by correcting a contour of a video signal of a natural picture image and the like from a computer. Video signals of, for example, three primary colors (R, G, B), including a natural picture image and the like produced by, for example, a computer from input terminals 1 are supplied to a mixing circuit (2) and mixed at a ratio of, for example, 0.6G+0.3R+0.1B to produce a signal corresponding to a luminance (Y). This signal is supplied to differentiation circuits 3A and 3B having different time constants each other and predetermined high frequency components are extracted therefrom, respectively, and these output signals are selected by a switch (4), and then supplied to an amplifying circuit 5. The gain of the amplifying circuit 5 is arbitrarily controlled by a signal from a control terminal (6).

Abstract: Disclosed is a register file used in a multiprocessor composition composed of a plurality of processor elements, the register file having a plurality of words and being provided for each of the plurality of processor elements, wherein: the plurality of words are divided into a word part that can be simultaneously accessed by some of the plurality of processor elements to use in common with other processor element, and a word part that can be accessed only by its own processor element.

Abstract: An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the augend signal bits, the addend signal bits and the carry bits supplied from lower-digits, a carry propagation block responsive to control signal bits for dividing the adder into partial adders and having propagation stages for producing carry signal bits from the carry generation signal bits, the carry propagation signal bits and the control signal bits, and a sum generation block for producing sum signal bits from the carry propagation signal bits, the control signal bits and the carry signal bits, and is divisible into an arbitrary number of partial adders without increase the stages of a critical path.

Abstract: A semiconductor device includes: a plurality of first field effect transistors (FETs) having a gate formed on a main surface of a semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; a plurality of second FETs having a gate formed on the main surface of the semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; and an electrically conductive layer that penetrates the main surface and a back surface of the semiconductor substrate in a region between the pair of FETs; wherein the first and second FETs that form the pair of FETs are disposed close to each other so that their drains are opposite to each other; wherein region widths of the first and second FETs in a direction of shorter sides of sources thereof are substantially identical with region widths of the first and second FETs in a direction of shorter sides of drains thereof; wherein all the drains of the first and second FETs are electrically connected to each other; where

Abstract: A transparent conductive film is formed on an outer surface of a face portion of a face panel and a phosphor screen is formed on an inner surface thereof. A conductive explosion proof band is wound around an outer periphery of a skirt portion of the face panel and the explosion proof band has a grounding potential. A conductive tape is attached along a long side of the face panel and electrically connects the transparent conductive film with the explosion proof band. A compensating electrode extending along a side of the face panel is attached to an upper side of the skirt portion and disposed on a side opposite to the conductive tape with respect to the explosion proof band. An inverse voltage applying portion applies a voltage having a waveform of a polarity inverse to that of the deflection voltage applied to a deflection device to the compensating electrode so as to generate an electric field for canceling an alternating electric field generated from the deflection device.

Abstract: There are disclosed a foamable composition which comprises (A) a vinyl chloride resin, (B) an inorganic substance containing inorganic fibers of not less that 1 .mu.m diameter, (C) a solvent having properties such that when a mixture, which is composed of 100 parts by weight of a vinyl chloride resin of average polymerization degree of 2400, 100 parts by weight of the solvent, and 6 parts by weight of dibasic lead stearate, is kneaded using a plastograph at 30 rpm while raising the temperature it exhibits a maximum torque of 4 to 25 N.m on the kneader, and (D) a decomposition-type blowing agent; and a process for preparing such; a rigid, foamed article made therefrom; and a process for preparing such article. Since the rigid, foamed article of the invention does not contain asbestos, it is not injurious to human safety and health.

Abstract: A method of and apparatus for setting the direction of a parabolic antenna towards a broadcasting satellite, suitable for use in the case where a plurality of satellites are available for service. The elevation angle and the azimuth angle of the antenna with respect to each satellite are minutely adjusted while the state of receiving of waves from the satellite is watched, and the values of the elevation and azimuth angles for each satellite are stored in a memory section when the optimum state of receiving is attained. When the user selects one of the satellites through a selecting section, a control section operates to activate a driving section to swing the antenna vertically and horizontally in accordance with the stored optimum data, thus directing the antenna correctly towards the designated satellite.

Abstract: An apparatus and a method of positioning pallets on roller chains mounted on a free flow conveyor is basically composed of a detector for detecting an oncoming pallet, a stopper for stopping the pallet at an approximately required position, a controller capable of positioning the pallet in the x- and y-directions, and another controller capable of positioning the pallet in the z-direction. With an application of the foregoing method proposed, a device is designed to provide a highly accurate positioning of the pallet with a single device and therefore contributes greatly to an economization of operating costs.

Abstract: A free flow conveyor which conveys in order a plurality of pallets freely loaded on roller chains in a required direction comprises a conveying feed path for the pallets to be defined at a first horizontal elevational level, another conveying return path for the pallets to be defined therebelow, and roller chains, to be mounted on both sides of the conveying paths, being endlessly wound in common with both feed and return paths so that the roller chains can be commonly driven. This invention will therefore provide a simple mechanism and a reduction in operating costs so as to eliminate the disadvantages of a free flow conveyor to which the prior art pertains.

Abstract: A credit transaction processing system processes data related to a commodity entered into by using a card (17) owned by a customer and a recording card (16) owned by a store. First, merchant transaction data necessary for a credit sale stored in the recording medium (16), such as account number data for the store, data specifying a credit company, and data representing an upper limit of an amount to to be sold through a credit sale, are read by a card reader (5), and then, customer transaction data stored in the customer's recording card, such as account number data of the customer, data specifying a credit company and an identification number or code is read. If and when the customer enters his identification number by a ten-key (7), a central processing unit (12) determines whether the entered identification number coincides with the identification number read out of the customer's card.

Abstract: A credit transaction processing system processes data related to a commodity entered into by using a card (17) owned by a customer and a recording card (16) owned by a store. First, merchant transaction data necessary for a credit sale stored in the recording medium (16), such as account number data for the store, data specifying a credit company, and data representing an upper limit of an amount to to be sold through a credit sale, are read by a card reader (5), and then, customer transaction data stored in the customer's recording card, such as account number data of the customer, data specifying a credit company and an identification number or code is read. If and when the customer enters his identification number by a ten-key (7), a central processing unit (12) determines whether the entered identification number coincides with the identification number read out of the customer's card.