Patents by Inventor Toshiaki Kitamura

Toshiaki Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200233669
    Abstract: A processor system (200) includes one task execution unit (220), another task execution unit (250), and a flag storage unit (230) provided with a control unit (232) and a flag area (234). When flag information stored in the flag area (234) does not satisfy a predetermined condition, the one task execution unit (220) outputs, to the control unit (232), a signal indicating that the flag information is being monitored, and suspends access to the flag information. The control unit (232) monitors the presence or absence of access to the flag information from the other task execution unit (250), and when there is access to the flag information, the control unit (232) outputs, to the one task execution unit (220), an instruction to release the suspension of access to the flag information.
    Type: Application
    Filed: February 16, 2017
    Publication date: July 23, 2020
    Inventors: Toshiaki Kitamura, Takashi Mochiyama
  • Patent number: 7355379
    Abstract: A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma generating method includes controlling the impedance matching device, when the plasma is generated in the treating chamber, so as to satisfy a preset matching condition, and then controlling the high-frequency generating unit to generate and feed the high-frequency signal of the power generating the plasma, to the treating chamber.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 8, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Patent number: 7176634
    Abstract: A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma generating method includes controlling the impedance matching device, when the plasma is generated in the treating chamber, so as to satisfy a preset matching condition, and then controlling the high-frequency generating unit to generate and feed the high-frequency signal of the power generating the plasma, to the treating chamber.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 13, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Publication number: 20060144519
    Abstract: A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma generating method includes controlling the impedance matching device, when the plasma is generated in the treating chamber, so as to satisfy a preset matching condition, and then controlling the high-frequency generating unit to generate and feed the high-frequency signal of the power generating the plasma, to the treating chamber.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 6, 2006
    Applicant: Tokyo Electron Limited
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Publication number: 20050057164
    Abstract: A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma generating method includes controlling the impedance matching device, when the plasma is generated in the treating chamber, so as to satisfy a preset matching condition, and then controlling the high-frequency generating unit to generate and feed the high-frequency signal of the power generating the plasma, to the treating chamber.
    Type: Application
    Filed: September 27, 2004
    Publication date: March 17, 2005
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Patent number: 6856211
    Abstract: A coaxial type impedance matching device includes a matching device body including an external conductor and an internal conductor arranged in the external conductor, an input side dielectric disposed in the matching device body and including a first dielectric and a second dielectric, and an output side dielectric disposed in the matching device body and including a third dielectric and a fourth dielectric. Distance between opposed surfaces of the first dielectric and the second dielectric is a predetermined distance, which is in a range of N?/4??/6 to N?/4??/6, where ? represents a guide wavelength of an input signal in the matching device body and N represents odd number. Distance between opposed surfaces of the third dielectric and the fourth dielectric is the predetermined distance.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: February 15, 2005
    Assignees: Nagano Japan Radio Co., Ltd., Tokyo Electron Limited
    Inventors: Fumio Yamada, Toshiaki Kitamura, Hiroyuki Kobayashi, Koichi Rokuyama, Akihiro Kubota, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Patent number: 6819052
    Abstract: For plasma generation, an impedance matching device and a process of controlling and detecting the impedance matching device are provided to satisfy a preset matching condition. The impedance matching device includes a tubular external conductor and an internal conductor disposed therein, a matching device body including a plurality of dielectrics, a moving mechanism, a storing unit for storing a data table, a measuring device, and a calculation control unit. The impedance detecting process includes inputting a progressive wave and a reflected wave outputted by a directional coupler connected to an object to be matched, generating different signals, and mixing the signals to determine relative phase differences and amplitude ratios of the signals, and detecting an input impedance of the object to be matched on a basis of the detected amplitude ratios and that of a true phase difference between the progressive wave and the reflected wave that is detected by referring to a relationship prepared in advance.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: November 16, 2004
    Assignees: Nagano Japan Radio Co., Ltd., Tokyo Electron Limited
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Publication number: 20040023561
    Abstract: A coaxial type impedance matching device includes a matching device body including an external conductor and an internal conductor arranged in the external conductor, an input side dielectric disposed in the matching device body and including a first dielectric and a second dielectric, and an output side dielectric disposed in the matching device body and including a third dielectric and a fourth dielectric. Distance between opposed surfaces of the first dielectric and the second dielectric is a predetermined distance, which is in a range of N&lgr;/4−&lgr;/6 to N&lgr;/4−&lgr;/6, where &lgr; represents a guide wavelength of an input signal in the matching device body and N represents odd number. Distance between opposed surfaces of the third dielectric and the fourth dielectric is the predetermined distance.
    Type: Application
    Filed: May 20, 2003
    Publication date: February 5, 2004
    Inventors: Fumio Yamada, Toshiaki Kitamura, Hiroyuki Kobayashi, Koichi Rokuyama, Akihiro Kubota, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Publication number: 20030230984
    Abstract: A plasma generating method generates plasma in a treating chamber by controlling a high-frequency generating unit to generate a high-frequency signal and by feeding the high-frequency signal to the treating chamber through an impedance matching device. The plasma generating method includes controlling the impedance matching device, when the plasma is generated in the treating chamber, so as to satisfy a preset matching condition, and then controlling the high-frequency generating unit to generate and feed the high-frequency signal of the power generating the plasma, to the treating chamber.
    Type: Application
    Filed: May 20, 2003
    Publication date: December 18, 2003
    Inventors: Toshiaki Kitamura, Koichi Rokuyama, Shigeru Kasai, Takashi Ogino, Yuki Osada
  • Patent number: 6519730
    Abstract: Disclosed is a computer in which an error caused by an intermittent failure is corrected by using a misprediction recovery mechanism which performs recovery processing if, after having predicted a branch destination of a branch instruction and speculatively executed an instruction at the predicted branch destination, it turns out that the branch prediction was wrong. The computer includes an error detection mechanism for detecting an error in logic operation of the computer, and an instruction re-execution mechanism for correcting an error caused by an intermittent failure when an error is detected by the error detection mechanism, by restoring the computer, using the misprediction recovery mechanism, to a state that existed before the occurrence of the error, and by re-executing a sequence of instructions including the instruction where the error is detected.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: February 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Hisashige Ando, Toshiaki Kitamura, Michael Shebanow, Michael Butler
  • Patent number: 6512578
    Abstract: A surface inspection apparatus of the present invention comprises: an illumination optical system 100 which is fixed at a first predetermined angle with respect to a wafer 3 and which irradiates a substantially parallel illuminating light toward the entire surface of the wafer 3; an image pickup device 6 which is fixed at a second predetermined angle with respect to the wafer 3 and which receives diffracted light or scattered light from the wafer 3 and projects an image of the wafer; and an image processing apparatus 7 which performs a macro inspection by taking the image signal generated by the image pickup device 6 and carrying out image processing, and is further provided with a plurality of interference filters F1˜F4 to enable the variable setting of the wavelength of the illuminating light from the illumination optical system 100.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: January 28, 2003
    Assignee: Nikon Corporation
    Inventors: Koichiro Komatsu, Takeo Omori, Toshiaki Kitamura
  • Patent number: 5373567
    Abstract: In the pattern matching method, when a reference pattern is extracted from the reference picture, check search is carried out repeatedly a plural number of times while conducting picture compressions on the reference picture with the compression start position being changed to obtain correlation values between the reference picture and the reference pattern. Based on the correlation values obtained by the check search, the number of times of search to be done actually and the picture compression ratio for the actual search are determined.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: December 13, 1994
    Assignee: Nikon Corporation
    Inventors: Kozo Takahashi, Toshiaki Kitamura, Muneki Hamashima
  • Patent number: 5369430
    Abstract: A focus detecting method includes the step of projecting the real image of an observation object including a plurality of object patterns onto an image pickup device through an optical system and producing image data from an output of the image pickup device, the step of calculating correlation values of the image data of each of the plurality of object patterns and the image data of a prestored reference pattern while varying the relative positional relation among the image pickup device, the optical system and the observation object in the direction of the optical axis of the optical system, and the step of judging a relative positional relation giving the maximum correlation value as an in-focus state. An apparatus is provided for carrying out the above-described focus detecting method.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: November 29, 1994
    Assignee: Nikon Corporation
    Inventor: Toshiaki Kitamura
  • Patent number: 5179693
    Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse sets a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.
    Type: Grant
    Filed: October 3, 1989
    Date of Patent: January 12, 1993
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Kazuyuki Shimizu, Yuji Oinaga, Katsumi Onishi
  • Patent number: 5043868
    Abstract: A system for computer pipeline operation in which a plurality of instructions are executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, including a conflict detection unit, a data establishment indication unit, and a source data by-pass unit. The source data by-pass unit by-passes a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.
    Type: Grant
    Filed: December 19, 1989
    Date of Patent: August 27, 1991
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Yuji Oinaga, Katsumi Onishi
  • Patent number: 4910671
    Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.
    Type: Grant
    Filed: March 27, 1986
    Date of Patent: March 20, 1990
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Kazuyuki Shimizu, Yuji Oinaga, Katsumi Onishi
  • Patent number: 4870567
    Abstract: The present invention includes a suboperation code control memory which stores data for generating a heading address of a microprogram for an instruction having a suboperation code. Access to an operation code control memory by the ordinary operation code and the access to suboperation code control memory are carried out simultaneously. The heading address of the microprogram is generated by editing the data read from the respective control memories. The storage capacity needed for the suboperation memory is reduced and still no problem occurs in assigning microinstruction addresses, and the heading address of a microprogram for the instruction having a relevant suboperation code is produced without any additional time.
    Type: Grant
    Filed: June 25, 1985
    Date of Patent: September 26, 1989
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Katsumi Onishi
  • Patent number: 4812970
    Abstract: According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed.
    Type: Grant
    Filed: July 25, 1985
    Date of Patent: March 14, 1989
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Katsumi Onishi, Yuji Oinaga
  • Patent number: 4701915
    Abstract: An error recovery system in a data processor of the pipeline type, including control storage for storing instruction data, having an error correction and detection code adapted to the detection and correction of errors, for controlling the data processor. A parity check circuit checks instructions read from the control storage and stops at least a part of pipeline processing immediately upon the detection of an error. An error correction circuit corrects the error in the read instruction data and rewrites the instruction data into the control storage while the part of the pipeline processing is stopped.
    Type: Grant
    Filed: August 7, 1985
    Date of Patent: October 20, 1987
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Kitamura, Yuji Oinaga