Patents by Inventor Toshiaki Matsubara
Toshiaki Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6670844Abstract: A highly efficient charge pump circuit featuring easy circuit design and formation as well as high reliability includes transistors M1-M4 individually having a diode connection configuration and interconnected in cascade, and is adapted to alternately apply a clock signal and an inverted clock signal to the transistors via capacitor elements C1-C4. The charge pump employs a depression-type transistor as the transistors M1-M4 and has an arrangement wherein the transistors M1, M2 on an input side have a greater gate length than the succeeding transistors M3, M4 for increasing the efficiency of boosting voltage. The charge pump circuit includes a single type of device so as to facilitate the circuit design and formation and also to enhance the reliability thereof.Type: GrantFiled: September 4, 2002Date of Patent: December 30, 2003Assignee: Nippon Precision Circuits Inc.Inventors: Fumikazu Kobayashi, Shuuji Sakamoto, Toshiaki Matsubara
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Publication number: 20030058665Abstract: A highly efficient charge pump circuit featuring easy circuit design and formation as well as high reliability is provided. The charge pump circuit includes transistors M1-M4 individually having a diode connection configuration and interconnected in cascade, and is adapted to alternately apply a clock signal and an inverted clock signal to the transistors via capacitor elements C1-C4. The charge pump employs a depression-type transistor as the transistors M1-M4 and has an arrangement wherein the transistors M1, M2 on an input side have a greater gate length than the succeeding transistors M3, M4 for increasing the efficiency of boosting voltage. The charge pump circuit includes a single type of devices so as to facilitate the circuit design and formation and also to enhance the reliability thereof.Type: ApplicationFiled: September 4, 2002Publication date: March 27, 2003Inventors: Fumikazu Kobayashi, Shuuji Sakamoto, Toshiaki Matsubara
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Patent number: 5512847Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 6, 1994Date of Patent: April 30, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5495183Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: May 12, 1995Date of Patent: February 27, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Urragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5245224Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: March 3, 1992Date of Patent: September 14, 1993Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5103120Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: January 2, 1991Date of Patent: April 7, 1992Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5053909Abstract: Disclosed is a semiconductor integrated circuit device equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the input buffer portion, circuit elements for an output circuit disposed at the output buffer portion are used in order to constitute the input protection circuit.Type: GrantFiled: May 2, 1989Date of Patent: October 1, 1991Assignee: Hitachi, Ltd.Inventors: Yasunaga Suzuki, Toshiaki Matsubara, Akira Uragami
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Patent number: 5001487Abstract: A semiconductor integrated circuit device is disclosed. The circuit device uses modified (m+n) input cells, each equipped with high load driving functional elements disposed at the periphery of the cell, and having n signal input terminal(s) in addition to m normal signal input terminals that are incorporated in the cell.Type: GrantFiled: June 26, 1990Date of Patent: March 19, 1991Assignee: Hitachi, Ltd.Inventors: Yasunaga Suzuki, Toshiaki Matsubara, Haruo Mamyoda, Akira Uragami
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Patent number: 4983862Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 31, 1989Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4879480Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: September 2, 1988Date of Patent: November 7, 1989Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akiro Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4827368Abstract: A semiconductor integrated circuit device is provided which is equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the input buffer portion, circuit elements for an output circuit disposed at the corresponding output buffer portion are used in order to constitute the input protection circuit.Type: GrantFiled: September 16, 1987Date of Patent: May 2, 1989Assignee: Hitachi, Ltd.Inventors: Yasunaga Suzuki, Toshiaki Matsubara, Akira Uragami
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Patent number: 4710842Abstract: A semiconductor integrated circuit device is provided which is equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the corresponding input buffer portion, circuit elements for an output circuit disposed at the output buffer portion are used in order to constitute the input protection circuit. Therefore, the circuit elements of the corresponding output buffer portion, which normally would be unused, are utilized to provide an important circuit function.Type: GrantFiled: March 18, 1986Date of Patent: December 1, 1987Assignee: Hitachi, Ltd.Inventors: Yasunaga Suzuki, Toshiaki Matsubara, Akira Uragami
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Patent number: 4689503Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: January 31, 1984Date of Patent: August 25, 1987Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara