Patents by Inventor Toshiaki Matsuoka

Toshiaki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240109483
    Abstract: A lighting device includes a first light source portion, a light guide that includes a light guide body with an elongated shape, guides light incident from the first light source portion in a longitudinal direction of the elongated shape, and emits a first light including the guided light to illuminate an illuminated object, and a second light source portion that emits a second light to illuminate the illuminated object. The second light source portion is provided independently of the first light source portion and the light guide.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 4, 2024
    Inventors: Toshiaki MORI, Yoichi MATSUOKA, Koichiro ENDO, Akinori USHIJIMA, Isamu MASAKAWA, Jota KUSAKARI
  • Publication number: 20240109484
    Abstract: A lighting device includes a light source portion, a light guide that includes a light guide body with an elongated shape, guides light incident from the light source portion in a longitudinal direction of the elongated shape, and emits the light in an emission direction substantially orthogonal to the longitudinal direction, and a bezel that is provided along the light guide and includes an elongated-shaped opening through which the light emitted from the light guide passes and is emitted to the outside. The bezel includes at least one bridge portion that is formed along a lateral direction of the opening so as to partially bridge opposed walls of the opening in the lateral direction.
    Type: Application
    Filed: August 15, 2023
    Publication date: April 4, 2024
    Inventors: Toshiaki MORI, Yoichi MATSUOKA, Takao OKUMURA, Koichiro ENDO
  • Publication number: 20240101026
    Abstract: A lighting device includes a light source unit that outputs light, an elongated light guide including a first end surface on which the light is incident, a second end surface located opposite to the first end surface, an emitting surface, and at least one held portion provided on at least one of the longitudinal side surfaces different from the emitting surface, the light guide guiding the light from the first end surface to the second end surface, and a housing including an attachment portion to which the light source unit is attached, a housing portion that is open at an end portion on the attachment portion side and includes a housing recess to house the light guide and an exposure opening exposing the emitting surface, and a holding portion that holds the light guide in the housing recess by sandwiching the at least one held portion.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 28, 2024
    Inventors: Toshiaki MORI, Yoichi MATSUOKA, Koichiro ENDO, Yukihiko UMEDA, Shota KATSUNO, Hiroyuki ASANO
  • Publication number: 20150009240
    Abstract: A gamma reference voltages generating circuit with output offset for controlling a gray level of a light-emitting unit is provided. The light-emitting unit includes a switch and a light-emitting element which is coupled to a bias voltage. The gamma reference voltages generating circuit includes a first gamma voltage divider and a digital-to-analog converter. The first gamma voltage divider includes a plurality of resistors. A first terminal of the first gamma voltage divider is coupled to the bias voltage, and a second terminal of the first gamma voltage divider is coupled to a reference current source. The digital-to-analog converter is coupled to the first gamma voltage divider to receive a plurality of reference voltages generated by the first gamma voltage divider. The digital-to-analog converter is controlled by a digital control signal to output one of the reference voltages to a control terminal of the switch in the light-emitting unit.
    Type: Application
    Filed: August 23, 2013
    Publication date: January 8, 2015
    Applicant: INTEGRATED SOLUTIONS TECHNOLOGY INC.
    Inventors: TOSHIAKI MATSUOKA, CHIA CHENG LEI
  • Patent number: 6759019
    Abstract: A method for removing an acidic component such as sulfite gas (SO2) contained in an exhaust gas comprising by using a system comprising (a) a gas-liquid contact apparatus composed of an absorption column provided internally with at least one perforated plate at the top, bottom, or both top and bottom of the absorption column packed with at least one type of fillers, (b) an apparatus for introducing raw seawater to the absorption column, (c) an apparatus for oxidizing the seawater after gas-liquid contact, and (d) an apparatus for mixing raw seawater with the contact seawater after oxidation, whereby the exhaust gas containing an acidic component is brought into gas-liquid contact with the seawater.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: July 6, 2004
    Assignee: Fujikasui Engineering Co., Ltd.
    Inventors: Kouji Shiraishi, Takayoshi Harimoto, Toshiaki Matsuoka, Naoki Fujihata, Akihiko Hongyou, Katsuo Oikawa, Kazuo Takeda
  • Patent number: 6294951
    Abstract: A time domain filter circuit is provided with a switch for prohibiting inputting for the time between a change of an input signal and discharging a capacitor to 0, prior to a monostable multivibrator, so that a change of the next input signal is not accepted for a fixed time period since the input signal has been inverted. The time domain filter circuit detects a change of an input signal relative to an output signal, and detects a predetermined fixed time period based on the timing of the change by the monostable multivibrator using a charging time constant of the capacitor, so that an output signal level is changed so as to correspond to the input signal after the predetermined fixed time period elapses.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: September 25, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiaki Matsuoka
  • Patent number: 6198343
    Abstract: The current mirror circuit in accordance with the present invention includes a first current mirror circuit composed of first and second MOS transistors being cascade connected to a second current mirror circuit composed of third and fourth MOS transistors. Further, an NPN transistor is interposed between the gate and the drain of the third MOS transistor to which an input current is supplied. Thus, the third MOS transistor can operate normally even with a higher input voltage than in a case where the drain is connected to the gate by as much as the base-emitter voltage of the NPN transistor. In addition, even if the input current is in an off state, electric charge always flows out via the gates of the first and second MOS transistors as the base current of the NPN transistor. Thus, a current mirror circuit can be offered with high precision in output current and a short rise-time when changed from an on state to an off state, while maintaining a wide input voltage range.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: March 6, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiaki Matsuoka