Abstract: A motor control apparatus that applies a pulse voltage for each phase of a three phase brushless motor to make current flow, the apparatus provided with: a generating unit for causing the pulse voltage to be generated by shifting the phase of the pulse voltage for each phase of the three phase brushless motor; and a detecting unit for detecting a current flowing to a coil of each phase of the three phase brushless motor to which the pulse voltage is applied by switching by a predetermined sampling period for each phase one-by-one, wherein a relationship between the sampling period of the detecting unit and a phase shift amount of the pulse voltage of each phase generated by the generating unit is set so that the detecting unit can detect the current for each phase of the three phase brushless motor.

Abstract: A motor control apparatus that applies a pulse voltage for each phase of a three phase brushless motor to make current flow, the apparatus provided with: a generating unit for causing the pulse voltage to be generated by shifting the phase of the pulse voltage for each phase of the three phase brushless motor; and a detecting unit for detecting a current flowing to a coil of each phase of the three phase brushless motor to which the pulse voltage is applied by switching by a predetermined sampling period for each phase one-by-one, wherein a relationship between the sampling period of the detecting unit and a phase shift amount of the pulse voltage of each phase generated by the generating unit is set so that the detecting unit can detect the current for each phase of the three phase brushless motor.

Abstract: Systems, methods, and programs store a plurality of combinations of departure points and destination points that have been set in the past, store pre-update map information, and store post-update map information. The systems, methods, and programs compare, for each of the combinations of departure points and destination points, a route retrieved using the pre-update map information and a route retrieved using the post-update map information, and transmit the comparison results to the navigation apparatus so that a user of the navigation apparatus can appreciate the benefits of updating map information.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: Systems, methods, and programs, store map data including a roadway network, detect a current position of the vehicle, and detect or receive at lest one of a distance to another vehicle, a speed of another vehicle, and traffic congestion information. The systems, methods, and programs determine whether the vehicle is within a predetermined distance of a passing lane, a climbing lane, or a lane for slower traffic based on the detected current vehicle position and the map data. If the vehicle is within the predetermined distance, the systems, methods, and programs provide guidance regarding the passing lane, the climbing lane, or the lane for slower traffic based on at least one of the distance to the other vehicle, the speed of the other vehicle, and/or the received traffic congestion information.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: To provide a pyrrolidine analogue having an inhibitory activity on the induction of allodynia, a method for producing the pyrrolidine analogue, and an agent for preventing a neurogenic pain. A pyrrolidine analogue which is a compound represented by the general formula (I) [wherein HOOC-? represents an aromatic substituent having at least one carboxy group attached to the benzene ring] or a salt or ester of the compound. The compound has a potent inhibitory effect on the induction of allodynia.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: In a network regulated so that the unique identification information for a basic storage apparatus and that of each of a plurality of additional storage apparatuses do not overlap, the storage apparatuses can be connected to the network without being assigned unique identification information. The basic storage apparatus judges, when an additional storage apparatus is powered-on, whether or not an initial value is set in an identification information setting unit in the additional storage apparatus, the identification information setting unit being where unique identification information in the network is set. If it is judged that an initial value is set in the identification information setting unit, the basic storage apparatus enters a first mode in which it creates unique identification information, replaces the initial value with the created identification information, and recognizes the created identification information as unique identification information in the network.

Abstract: Proposed is a storage controller and its control method for speeding up the processing time in response to a command in a simple manner while reducing the load of a controller that received a command targeting a non-associated logical volume. This storage controller includes a plurality of controllers for controlling the input and output of data to and from a corresponding logical unit based on a command retained in a local memory, and the local memory stores association information representing the correspondence of the logical units and the controllers and address information of the local memory in each of the controllers of a self-system and another-system.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A memory control apparatus generates a plurality of commands whose unit of data transfer is smaller than the unit of data transfer of a memory access request, and when the memory access requests are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request source. The plurality of memory access requests are executed by time division and concurrently.

Abstract: When a display map information is reduced to a specified scale for a wide area, items of congestion information are extracted which have a congestion level of “congested or busy”, and an overlap determination area is created for a congestion link of each item of extracted congestion information. The overlap determination area extends both transversely and longitudinally for a specified distance from the congestion link. Also, for each group of congestion information items having overlapping determination areas, an equal congestion level area is created by connecting the overlap determination areas and displayed in a color that corresponds to the congestion level. Equal congestion level areas are also created in the same manner for the congestion information items with congestion levels of “congested” and “not congested”, and displayed in different colors that correspond to their respective congestion levels.

Abstract: A processor transfers control information set for each connection from a second memory to a first memory, and updates the control information stored in the first memory in accordance with processing of the connection. The processor selects control information updated in the first memory, and transfers the selected control information from the first memory to the second memory.

Abstract: A memory control apparatus generates a plurality of commands whose unit of transfer is smaller than the unit of data transfer of a memory access request, and when the memory access request are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request are executed by time division and concurrently.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: [Problems] To provide a pyrrolidine analogue having an inhibitory activity on the induction of allodynia, a method for producing the pyrrolidine analogue, and an agent for preventing a neurogenic pain. [Means for Solving the Problems] A pyrrolidine analogue which is a compound represented by the general formula (I) [wherein HOOC-? represents an aromatic substituent having at least one carboxy group attached to the benzene ring] or a salt or ester of the compound. The compound has a potent inhibitory effect on the induction of allodynia.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.