Abstract: A timing generator for a semiconductor test system having an interleave architecture with no interleave jitters. The timing generator includes a plurality of timing data generators arranged in a parallel fashion and provided with a first clock signal in which each of the timing data generator produces a coarse timing signal and a delay time data based on timing data provided by a test program, a multiplexer provided with a second clock signal having a frequency higher than the first clock signal for receiving the coarse timing signals and delay data in parallel and produces selected one of coarse timing signal and the delay data in series, and a variable delay circuit which receives the coarse timing signal and the delay data from the multiplexer for providing a delay time defined by the delay data to the coarse timing signal.

Abstract: A clocked logic circuit operates in synchronism with a clock and is supplied with an input binary signal asynchronously with the clock for issuing an output binary signal. A phase detector circuit produces a phase difference signal indicating into which of k divided phase regions of one period of the clock falls, the phase difference between the input binary signal and the clock. The phase difference signal is delayed by a matching delay means for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.