Abstract: A structure and a method capable of both packing data into and unpacking data from either the little endian or the big endian format are provided. Under the structure and method of the present invention, the packed or unpacked data, as the case may be, is only shifted in one direction. During a packing operation, a stream of n-bit data is packed into a stream of m-bit words. During an unpacking operation, a stream of m-bit packed data is unpacked into a stream of n-bit words. n.ltoreq.m.

Abstract: In accordance with the present invention, a structure and a method for asynchronously interfacing a master processor and a slave processor is provided by receiving from and providing to the master device control signals of a polling protocol, and receiving from and providing to the slave device control signals of an interrupt type protocol. In a first embodiment of this invention, the master processor provides WR (write request), RD (read request), OE (output enable) signals, and receives a BUSY (busy) signal. The slave processor receives an "int" (interrupt) signal, and provides "intack" (interrupt acknowledge), "outs" (output), and "ins" (input) signals. In a second embodiment of this invention, instead of the RD signal of the first embodiment, the read request signal is the AND product of an AS (address strobe) signal and the most significant bit of the read address.

Abstract: A circuit for precharging a bus has a first bus and a second bus separately and first and second driving MOS transistors respectively driving the first and second buses, and is so structured that a signal inputted to the first bus is transmitted to the gate of the second driving MOS transistor through a CMOS inverter to thereby drive the second bus and that a signal inputted to the second bus is transmitted to the gate of the first driving MOS transistor through another CMOS inverter to thereby drive the first bus. In this manner, a signal inputted to either of these buses causes these buses to be combined nonsynchronously.