Patents by Inventor Toshiaki Morita

Toshiaki Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847614
    Abstract: A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 24, 2020
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tomoyasu Furukawa, Toshiaki Morita, Daisuke Kawase, Toshihito Tabata
  • Patent number: 10763346
    Abstract: Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: September 1, 2020
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tomoyasu Furukawa, Masaki Shiraishi, Toshiaki Morita
  • Publication number: 20200075722
    Abstract: A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.
    Type: Application
    Filed: June 24, 2019
    Publication date: March 5, 2020
    Inventors: Tomoyasu FURUKAWA, Toshiaki MORITA, Daisuke KAWASE, Toshihito TABATA
  • Publication number: 20200006301
    Abstract: Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced.
    Type: Application
    Filed: December 25, 2017
    Publication date: January 2, 2020
    Inventors: Tomoyasu FURUKAWA, Masaki SHIRAISHI, Toshiaki MORITA
  • Patent number: 10522638
    Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 31, 2019
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Masakazu Sagawa, Takahiro Morikawa, Motoyuki Miyata, Kan Yasui, Toshiaki Morita
  • Publication number: 20190157412
    Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.
    Type: Application
    Filed: October 5, 2018
    Publication date: May 23, 2019
    Inventors: Masakazu SAGAWA, Takahiro MORIKAWA, Motoyuki MIYATA, Kan YASUI, Toshiaki MORITA
  • Patent number: 10177069
    Abstract: A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding member; or a semiconductor module formed by bonding a semiconductor chip, a metal wire, a ceramic insulating substrate, and a heat-dissipating base substrate including metal, with a die bonding member interposed between each. At least one of the die bonding members includes a lead-free low-melting-point glass composition and metal particles. The lead-free low-melting-point glass composition accounts for 78 mol % or more in terms of the total of the oxides V2O5, TeO2, and Ag2O serving as main ingredients. The content of each of TeO2 and Ag2O is 1 to 2 times the content of V2O5, and at least one of BaO, WO3, and P2O5 is included as accessory ingredients, and at least one of Y2O3, La2O3, and Al2O3 is included as additional ingredients.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 8, 2019
    Assignee: HITACHI LTD.
    Inventors: Takashi Naito, Motomune Kodama, Takuya Aoyagi, Shigeru Kikuchi, Takashi Nogawa, Mutsuhiro Mori, Eiichi Ide, Toshiaki Morita, Akitoyo Konno, Taigo Onodera, Tatsuya Miyake, Akihiro Miyauchi
  • Publication number: 20170278589
    Abstract: Provided are: a sintering binder including nanoparticles, a method for producing the sintering binder, and a method for bonding using the sintering binder. The sintering binder mainly includes cuprous oxide nanoparticles, combines particle stability with bondability, and less undergoes ion migration. A composite particle including metallic copper with the remainder being cuprous oxide and inevitable impurities is used for bonding typically of metals. The composite particle structurally includes metallic copper dispersed inside the particle and has an average particle size of 1000 nm or less.
    Type: Application
    Filed: November 18, 2015
    Publication date: September 28, 2017
    Applicant: HITACHI, LTD.
    Inventors: Yusuke YASUDA, Toshiaki MORITA, Yoshio KOBAYASHI, Takafumi MAEDA
  • Publication number: 20170236768
    Abstract: A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding member; or a semiconductor module formed by bonding a semiconductor chip, a metal wire, a ceramic insulating substrate, and a heat-dissipating base substrate including metal, with a die bonding member interposed between each. At least one of the die bonding members includes a lead-free low-melting-point glass composition and metal particles. The lead-free low-melting-point glass composition accounts for 78 mol % or more in terms of the total of the oxides V2O5, TeO2, and Ag2O serving as main ingredients. The content of each of TeO2 and Ag2O is 1 to 2 times the content of V2O5, and at least one of BaO, WO3, and P2O5 is included as accessory ingredients, and at least one of Y2O3, La2O3, and Al2O3 is included as additional ingredients.
    Type: Application
    Filed: September 9, 2015
    Publication date: August 17, 2017
    Applicant: HITACHI, LTD.
    Inventors: Takashi NAITO, Motomune KODAMA, Takuya AOYAGI, Shigeru KIKUCHI, Takashi NOGAWA, Mutsuhiro MORI, Eiichi IDE, Toshiaki MORITA, Akitoyo KONNO, Taigo ONODERA, Tatsuya MIYAKE, Akihiko MIYAUCHI
  • Publication number: 20160254761
    Abstract: A semiconductor device includes a semiconductor substrate in which a semiconductor element is formed, an electrode structure of a first semiconductor chip which is provided on a first surface of an n+-type semiconductor layer of the semiconductor substrate to be electrically connected to the semiconductor element and in which a first Al metal layer composed of Al or Al alloy, a Cu diffusion-prevention layer, a second Al metal layer composed of Al or Al alloy, and a Ni layer are formed in this order, and a conductive member which is bonded to the electrode structure of the first semiconductor chip via a sintered copper layer disposed on a surface of the Ni layer. In this semiconductor device, a crystal plane orientation of Al crystal grains on a surface of the second Al metal layer is principally on (110) plane.
    Type: Application
    Filed: February 24, 2016
    Publication date: September 1, 2016
    Inventors: Tomoyasu FURUKAWA, Masaki SHIRAISHI, Hiroshi NAKANO, Toshiaki MORITA
  • Patent number: 9404010
    Abstract: An object of the present invention is to provide a method for forming a multilayer coating film, capable of achieving excellent curability under low-temperature, short-time conditions, and forming a multilayer coating film having excellent chipping resistance and an excellent finished appearance. This method comprises sequentially applying an aqueous first colored coating composition (X), an aqueous second colored coating composition (Y), and a clear coating composition (Z) to a substrate, and simultaneously bake-curing the resulting multilayer coating film. In this method, the aqueous first colored coating composition (X) comprises an aqueous film-forming resin (A) and a specific blocked polyisocyanate compound (B), and the clear coating composition (Z) comprises a hydroxy-containing acrylic resin (K) having a hydroxy value in a specific range, a polyisocyanate compound (L), and an organometallic catalyst (M) containing a metal compound (M1) selected from a specific range and an amidine compound (M2).
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 2, 2016
    Assignee: KANSAI PAINT CO., LTD.
    Inventors: Naoyuki Iwata, Fumio Yamashita, Minoru Ishikura, Takashi Nakayabu, Kazushi Konishi, Toshiaki Morita, Masami Kobata
  • Publication number: 20150221626
    Abstract: A power semiconductor module includes a heat sink; a circuit board connected to the heat sink via a bonding material and formed with a wiring on a front surface of an insulating substrate; a transistor device including a main electrode and a control electrode formed on one surface and a back surface electrode formed on the other surface, the back surface electrode being connected to the circuit board via a bonding material; a first conductive member bonded to the main electrode via a bonding material; and wire or ribbon-shaped connection terminals that electrically connect the first conductive member and the control electrode with another device or the circuit board, wherein the control electrode is disposed at a corner portion of the main electrode, and the first conductive member has a shape in which the first conductive member is cut out at a portion above the control electrode.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 6, 2015
    Inventors: Shigehisa MOTOWAKI, Hiroshi HOZOJI, Toshiaki MORITA, Akitoyo KONNO
  • Publication number: 20150218405
    Abstract: An object of the present invention is to provide a method for forming a multilayer coating film, capable of achieving excellent curability under low-temperature, short-time conditions, and forming a multilayer coating film having excellent chipping resistance and an excellent finished appearance. This method comprises sequentially applying an aqueous first colored coating composition (X), an aqueous second colored coating composition (Y), and a clear coating composition (Z) to a substrate, and simultaneously bake-curing the resulting multilayer coating film. In this method, the aqueous first colored coating composition (X) comprises an aqueous film-forming resin (A) and a specific blocked polyisocyanate compound (B), and the clear coating composition (Z) comprises a hydroxy-containing acrylic resin (K) having a hydroxy value in a specific range, a polyisocyanate compound (L), and an organometallic catalyst (M) containing a metal compound (M1) selected from a specific range and an amidine compound (M2).
    Type: Application
    Filed: June 24, 2013
    Publication date: August 6, 2015
    Inventors: Naoyuki Iwata, Fumio Yamashita, Minoru Ishikura, Takashi Nakayabu, Kazushi Konishi, Toshiaki Morita, Masami Kobata
  • Patent number: 8912644
    Abstract: A semiconductor device includes an IGBT as a vertical semiconductor element provided between first, and second lead frames, in pairs, the first, and second lead frames being opposed to each other, first and second sintered-metal bonding layers provided on first and second bonding surfaces of the IGBT, in pairs, respectively, a through-hole opened in the second lead frame, and a heat-release member having a surface on one side thereof, bonded to a second sintered-metal bonding layer of the second bonding surface while a side (lateral face) of a surface of the heat-release member, on the other side thereof, being fitted into the through-hole. A solder layer is formed in a gap between an outer-side wall of the side of the surface of the heat-release member, on the other side thereof, and an inner-side wall of the through-hole.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 16, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Ide, Toshiaki Morita
  • Patent number: 8840811
    Abstract: The present invention provides a bonding material and a method of bonding for metal bonding at a bonding interface capable of a higher bonding strength at a lower temperature without application of pressure, compared to a bonding material of metal particles having an average particle size of not greater than 100 nm. An electrically conductive bonding material including (A) silver particles, (B) silver oxide, and (C) a dispersant including organic material containing not more than 30 carbon atoms as essential components, wherein a total amount of (A) the silver powder, (B) the silver oxide powder, and (C) the dispersant including an organic material containing not more than 30 carbon atoms is in a range of 99.0% to 100% by weight, is provided. In other words, no resin binder is contained.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: September 23, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yuusuke Yasuda, Toshiaki Morita, Eiichi Ide, Teiichi Inada
  • Patent number: 8821676
    Abstract: A bonding material comprising metal particles coated with an organic substance having carbon atoms of 2 to 8, wherein the metal particles comprises first portion of 100 nm or less, and a second portion larger than 100 nm but not larger than 100 ?m, each of the portions having at least peak of a particle distribution, based on a volumetric base. The disclosure is further concerned with a bonding method using the bonding material.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Patent number: 8821768
    Abstract: It is an object of this invention to provide a bonding material capable of realizing bonding by metallic bonding at a bonding interface at a lower temperature compared to a bonding material using a metal particle having an average particle diameter of not more than 100 nm and a bonding method. There is provided a bonding material including a metal particle precursor being at least one selected from the group consisting of a particle of a metal oxide, a particle of a metal carbonate, and a particle of a metal carboxylate and having an average particle diameter of 1 nm to 50 ?m and a reducing agent composed of an organic substance, wherein the content of the metal particle precursor is more than 50 parts by mass and not more than 99 parts by mass per 100 parts by mass of the bonding material.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: September 2, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Yasuda, Toshiaki Morita, Eiichi Ide, Hiroshi Hozoji, Toshiaki Ishii
  • Publication number: 20140147661
    Abstract: An aluminum salt is dissolved into water as a solvent to prepare an aqueous solution of the aluminum salt. Urea is added to the aqueous solution of the aluminum salt to be dissolved into the solution. The solution is heated to produce a precipitation of aluminum hydroxide. A deflocculant is added to deflocculate the precipitation. Thus, a sol is produced which contains colloidal particles of aluminum hydroxide and crystalline particles of aluminum oxide. An even and dense alumina thin film can be produced by using the sol on a surface of a substrate made of a metal having a low melting point, such as copper or aluminum.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 29, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Yusuke YASUDA, Toshiaki MORITA, Yoshio KOBAYASHI, Kazuhiro INOUE, Masachika HAMA
  • Patent number: 8635710
    Abstract: Optical information and topographic information of the surface of a sample are measured at a nanometer-order resolution and with high reproducibility without damaging a probe and the sample by combining a nanometer-order cylindrical structure with a nanometer-order microstructure to form a plasmon intensifying near-field probe having a nanometer-order optical resolution and by repeating approach/retreat of the probe to/from each measurement point on the sample at a low contact force.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Nakata, Masahiro Watanabe, Takashi Inoue, Kishio Hidaka, Makoto Okai, Toshiaki Morita, Motoyuki Hirooka
  • Patent number: 8592996
    Abstract: A semiconductor device wherein a semiconductor element made of Si or Si group material mounted on a substrate, the semiconductor element is mounted on the substrate and the semiconductor element is bonded to a silver bonding material via a oxide film formed on the semiconductor element. The bonding material comprising silver oxide particles having an average particle size of 1 nm to 50 nm and an organic reducing agent is used for bonding in air, which gives a high bonding strength to the oxide on the semiconductor element.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Morita, Yusuke Yasuda, Eiichi Ide