Abstract: A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.

Abstract: A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically connected to the first underlying lines, the first intermediate line including finger regions shaped like the first underlying lines, a coupling section to electrically interconnect the finger regions, a second intermediate line in the intermediate wiring layer electrically connected to the second underlying lines, the second intermediate line including finger regions shaped like the second underlying lines, and a coupling section to electrically connect the finger regions, a first overlying line in an overlying wiring layer electrically connected to the first intermediate line, and a second overlying line in the overlying wiring layer electrically connected t

Abstract: In a triangular-wave generating apparatus including an output terminal adapted to output an output voltage, an incorporated capacitor connected to the output terminal, a first variable current source adapted to charge the incorporated capacitor and a second variable current source adapted to discharge the incorporated capacitor, a charging/discharging current setting circuit sets a charging current in the first variable current source and sets a discharging current in the second variable current source. A level determining circuit determines whether or not the output voltage reaches one of predetermined voltages, to generate timing signals. A reference clock signal generating circuit generates a reference clock signal for defining a frequency of the output voltage. A charging/discharging current adjusting circuit adjusts the charging current and the discharging current in accordance with the timing signals and the reference clock signal.

Abstract: A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.

Abstract: In a current controlling apparatus for controlling a load current flowing through a load, a reference level generating circuit generates a reference level signal, and a reference signal generating circuit generates a reference signal in accordance with the reference level signal. A bridge circuit includes a plurality of semiconductor elements so that the semiconductor elements are turned ON and OFF to supply the load current to the load. A sensing circuit senses the load current, to thereby generate a sense signal in accordance with the load current. A current correction circuit including a correction comparator compares the sense signal with the reference level signal to generate a correction signal, so that the reference signal is corrected by the correction signal.

Abstract: A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals.

Abstract: A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically connected to the first underlying lines, the first intermediate line including finger regions shaped like the first underlying lines, a coupling section to electrically interconnect the finger regions, a second intermediate line in the intermediate wiring layer electrically connected to the second underlying lines, the second intermediate line including finger regions shaped like the second underlying lines, and a coupling section to electrically connect the finger regions, a first overlying line in an overlying wiring layer electrically connected to the first intermediate line, and a second overlying line in the overlying wiring layer electrically connected t

Abstract: A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals.

Abstract: In a triangular-wave generating apparatus including an output terminal adapted to output an output voltage, an incorporated capacitor connected to the output terminal, a first variable current source adapted to charge the incorporated capacitor and a second variable current source adapted to discharge the incorporated capacitor, a charging/discharging current setting circuit sets a charging current in the first variable current source and sets a discharging current in the second variable current source. A level determining circuit determines whether or not the output voltage reaches one of predetermined voltages, to generate timing signals. A reference clock signal generating circuit generates a reference clock signal for defining a frequency of the output voltage. A charging/discharging current adjusting circuit adjusts the charging current and the discharging current in accordance with the timing signals and the reference clock signal.

Abstract: In a current controlling apparatus for controlling a load current flowing through a load, a reference level generating circuit generates a reference level signal, and a reference signal generating circuit generates a reference signal in accordance with the reference level signal. A bridge circuit includes a plurality of semiconductor elements so that the semiconductor elements are turned ON and OFF to supply the load current to the load. A sensing circuit senses the load current, to thereby generate a sense signal in accordance with the load current. A current correction circuit including a correction comparator compares the sense signal with the reference level signal to generate a correction signal, so that the reference signal is corrected by the correction signal.

Abstract: When a rise of an input signal Vin is applied to an input terminal, an output of a two-input NAND circuit changes to the “H” level, and an output MOS transistor is controlled to turn off. In this state, a sense MOS transistor is simultaneously controlled to turn off, the electric potential of a drain of the sense MOS transistor is pulled down, an output of a two-input NOR circuit changes to the “H” level, and an output MOS transistor is controlled to turn on. When a fall of the input signal Vin is applied to the input terminal, the output of two-input NOR circuit changes to the “L” level, and the output MOS transistor is controlled to turn off. In this state, a sense MOS transistor is simultaneously controlled to turn off, the electric potential of a drain of the sense MOS transistor is pulled up, and the output of two-input NAND circuit changes to the “L” level, and the output MOS transistor is controlled to turn on.