Abstract: A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S2, a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S3, a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S4, an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S5, all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip.

Abstract: In the step (S11), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S12) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S11). After that, in the step (S13) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.

Abstract: A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S2, a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S3, a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S4, an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S5, all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip.

Abstract: In the step (S11), chip classification data in which a plurality of chips are classified into four sorts on the basis of presence/absence of (new) defects and pass/fail (of integrated circuits) is obtained. Next, in the step (S12) set is a situation where chips are randomly extracted out of all the chips with the number of chips with defect used as random extraction number on the basis of the chip classification data obtained in the step (S11). After that, in the step (S13) obtained is the random probability of failure (P(N4)) which is a probability that the number of faulty chips included in the randomly-extracted chips should be not less than the equivalent of the number (N4) of faulty chips with defect. Thus obtained is a defect analysis method and a method of verifying chip classification data, by which the analysis result on the basis of the chip classification data can be enhanced.

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: The alignment method allows a constant decision of an alignment point even with an indistinct outline of an alignment mark. An operator moves a chip (2) so that the whole or parts of an alignment mark (1) (including at least angles D0A0B0 and A0B0C0) is included within a lens view field (4), and then decides an alignment point (AP0). More specifically, the operator reads angles which are specified to obtain bisectors, from a defect inspection apparatus; obtains respective bisectors of the angles; and decides the intersection thereof to be the alignment point (AP0). Then, a stage drive required to superimpose the alignment point (AP0) on the center (O) is calculated on the basis of the shift amount between the position of the alignment point (AP0) and the center (O) of a target scope (5) displayed at the lens view field (4). The chip (2) is then moved by the stage drive.

Abstract: An inspection apparatus for foreign matter and pattern defects includes an optical portion (D) and an analyzer (AN). The optical portion (D) includes a microscope illumination optical system (D1) for detecting the surface of a semiconductor wafer (2) in the form of a piece of first surface information by using microscope illumination, and a laser scattering type optical system (D2) for detecting scattered laser light from the semiconductor wafer by using laser light to detect the surface of the semiconductor wafer (2) in the form of a piece of second surface information.

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle over (1)} non-defective chip with no new defect; {circle over (2)} defective chip with no new defect; {circle over (3)} non-defective chip with new defect; and {circle over (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

Abstract: An inspection apparatus for foreign matter and pattern defects includes an optical portion (D) and an analyzer (AN). The optical portion (D) includes a microscope illumination optical system (D1) for detecting the surface of a semiconductor wafer (2) in the form of a piece of first surface information by using microscope illumination, and a laser scattering type optical system (D2) for detecting scattered laser light from the semiconductor wafer by using laser light to detect the surface of the semiconductor wafer (2) in the form of a piece of second surface information.

Abstract: An inspection apparatus for foreign matter and pattern defects includes an optical portion (D) and an analyzer (AN). The optical portion (D) includes a microscope illumination optical system (D1) for detecting the surface of a semiconductor wafer (2) in the form of a piece of first surface information by using microscope illumination, and a laser scattering type optical system (D2) for detecting scattered laser light from the semiconductor wafer by using laser light to detect the surface of the semiconductor wafer (2) in the form of a piece of second surface information.

Abstract: The alignment method allows a constant decision of an alignment point even with an indistinct outline of an alignment mark. An operator moves a chip (2) so that the whole or parts of an alignment mark (1) (including at least angles D0A0B0 and A0B0C0) is included within a lens view field (4), and then decides an alignment point (AP0). More specifically, the operator reads angles which are specified to obtain bisectors, from a defect inspection apparatus; obtains respective bisectors of the angles; and decides the intersection thereof to be the alignment point (AP0). Then, a stage drive required to superimpose the alignment point (AP0) on the center (O) is calculated on the basis of the shift amount between the position of the alignment point (AP0) and the center (O) of a target scope (5) displayed at the lens view field (4). The chip (2) is then moved by the stage drive.

Abstract: The alignment method allows a constant decision of an alignment point even with an indistinct outline of an alignment mark. An operator moves a chip (2) so that the whole or parts of an alignment mark (1) (including at least angles D0A0B0 and A0B0C0) is included within a lens view field (4), and then decides an alignment point (AP0). More specifically, the operator reads angles which are specified to obtain bisectors, from a defect inspection apparatus; obtains respective bisectors of the angles; and decides the intersection thereof to be the alignment point (AP0). Then, a stage drive required to superimpose the alignment point (AP0) on the center (O) is calculated on the basis of the shift amount between the position of the alignment point (AP0) and the center (O) of a target scope (5) displayed at the lens view field (4). The chip (2) is then moved by the stage drive.