Patents by Inventor Toshiaki Nakahashi

Toshiaki Nakahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8258814
    Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Nakahashi
  • Publication number: 20110258589
    Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshiaki NAKAHASHI
  • Patent number: 7990179
    Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Nakahashi
  • Publication number: 20100301916
    Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 2, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Toshiaki NAKAHASHI