Abstract: In the present invention, when growing a silicon single crystal free of grown-in defects by the CZ method, the crystal is pulled out at or in a vicinity of a critical pulling rate at which a ring-shaped OSF occurrence region vanishes in a center portion of the crystal by using a hot zone structure in which a temperature gradient Gc in a center portion of the crystal is equal to or greater than a temperature gradient Ge in a peripheral portion of the crystal, while supplying an inert gas including hydrogen to an interior of a pulling furnace. By means of the present invention, the critical pulling rate at which the ring-shaped OSF occurrence region vanishes in the center portion of the crystal is increased, and single crystals free of grown-in defects in which dislocation clusters and COPs do not exist over the entire crystal radial direction in the as-grown state, can be grown by pulling at a pulling rate higher an that in the prior art.

Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3–1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.–1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ? of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost.

Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.

Abstract: Firstly, a silicon ingot in which boron and germanium were doped is sliced to prepare a silicon wafer and then the wafer is thermally processed by oxidation to form the thermal oxidation film on the surface layer portion of the wafer. Thereby, the concentration of germanium is enhanced in the vicinity of the interface with the thermal oxidation film of the wafer. Then, the thermal oxidation film is removed from the surface layer portion of the wafer. Further, an epitaxial layer consisting of a silicon single crystal in which a lower concentration of boron than the concentration of boron in the wafer was doped is grown on the shallow surface layer portion of the wafer by an epitaxial growth method. According to the present invention, the doping amount of germanium is reduced and the generation of misfit dislocations is suppressed.

Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: ?0.8×10?3?4.64×10?24×[Ge]?2.69×10?23×[B]?1.5×10?3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.

Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.

Abstract: A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1×1013 atoms/cm3-1×1015 atoms/cm3 with a cooling rate of not less than 2.5° C./min at a crystal temperature of 1150° C.-1000° C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than ⅗ of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9×1017 atoms/cm3 (ASTM '79).

Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: −0.8×10−3≦4.64×10−24×[Ge]−2.69×10−23×[B]≦1.5×10−3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.

Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 atoms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.

Abstract: The invention relates to a silicon wafer and an epitaxial silicon wafer, which are doped with arsenic (As) as an n-type dopant and are excellent in gettering characteristics. A first silicon wafer has a resistivity of 10 &OHgr;cm to 0.001 &OHgr;cm as a result of addition of arsenic and has a nitrogen concentration of 1×1013 to 1×1015 atoms/cm3. A second silicon wafer has a resistivity of 0.1 &OHgr;cm to 0.005 &OHgr;cm and a nitrogen concentration of 1×1014 to 1×1015 atoms/cm3. A third silicon wafer has a resistivity of 0.005 &OHgr;cm to 0.001 &OHgr;cm and a nitrogen concentration of 1×1013 to 3×1014 atoms/cm3. An epitaxial silicon wafer derived from any of the first to third silicon wafers by forming an epitaxial layer in the surface layer portion is provided.

Abstract: A method of producing high-quality epitaxial wafers with scarce occurrence of epitaxial layer defects by allowing an epitaxial layer on wafers sliced from a nitrogen-doped silicon single crystal as well as a method of pulling up a silicon single crystal to serve as the raw material therefore is provided. More particularly, a method of pulling up a single crystal from a nitrogen-doped silicon material melt while allowing the single crystal to grow is provided which comprises employing a passing or residence time in the temperature range of 1150-1050° C. of not less than 50 minutes and/or a passing or residence time in the temperature range of 1050-950° C. of not more than 40 minutes in the step of pulling up of the single crystal. Further, a method of manufacturing epitaxial wafers is provided which comprises allowing an epitaxial layer on the surface of silicon wafers sliced from the single crystal pulled up by the method mentioned above.

Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 at ms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.

Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.

Abstract: A method of producing high-quality epitaxial wafers with scarce occurrence of epitaxial layer defects by allowing an epitaxial layer on wafers sliced from a nitrogen-doped silicon single crystal as well as a method of pulling up a silicon single crystal to serve as the raw material therefore is provided. More particularly, a method of pulling up a single crystal from a nitrogen-doped silicon material melt while allowing the single crystal to grow is provided which comprises employing a passing or residence time in the temperature range of 1150-1050° C. of not less than 50 minutes and/or a passing or residence time in the temperature range of 1050-950° C. of not more than 40 minutes in the step of pulling up of the single crystal. Further, a method of manufacturing epitaxial wafers is provided which comprises allowing an epitaxial layer on the surface of silicon wafers sliced from the single crystal pulled up by the method mentioned above.

Abstract: Local irregularities in luminance are removed from a surface light source device of side light type 20 applied to a liquid crystal display or the like. In assembly, a reflection sheet 4 and a primary light source 23 are mounted on a light guide plate 2, and these components are housed at a predetermined position in a frame 21. The primary light source 23 has a fluorescent lamp 25 and a reflector 26, and supplied illumination light to an end surface (an incidence surface) 2A of the light guide plate 2. The reflector 26 presses the reflection sheet 4 against the light guide plate 2 and supports the reflection sheet. A support member 24 has a claw 24C engageable with a claw 21C of the frame 21. A light absorbable layer 27 is formed on an end portion of the reflection sheet 4.

Abstract: There is provided a surface light source device of side light type, which is not reduced in efficiency of illumination light utilization, even if the surface light source device is subjected to fringing such as to trim a luminant portion. For instance, a light shielding layer formed by coating black ink 21A, which absorbs illumination light, by means of printing is provided on a protection sheet 21 arranged as the outermost emission-side additional sheet. The light shielding layer absorbs and shields illumination light L1 tending to be transmitted through a peripheral edge portion of the protection sheet 12, and as a result, provides fringing. A reflective surface is formed by applying a silver tape 21B or the like to a surface facing the light guide plate 6. Since illumination light reflected by the silver tape 21B is used again inside the light guide plate 6, it is possible to avoid a reduction in efficiency of light utilization.

Abstract: In a surface light source device of side light type and a display employing the same, illumination light of high grade is allowed to emit by reducing irregularities in luminance caused along a muntin of a support member to support components such as a light guide plate 2 and a reflection sheet 21. A light quantity correction surface 21A is formed between the reflection member 21 and a support member 11. Otherwise, a member providing the light quantity correction surface is arranged on the rear of the support member. A quantity of illumination light in a portion of a muntin 11B of the support member 11 is made approximately equal to that in a portion of an aperture 11C, and the irregularities in luminance caused correspondingly to the muntin are reduced. The light quantity correction surface may be provided by a surface of the muntin itself or ink coated on the muntin by means of printing.

Abstract: An inexpensive, very fine wire of high-purity copper is disclosed as an alternative to the fine gold wire which is currently used in the bonding of semiconductor devices. The very fine wire of high-purity copper is prepared from a copper ingot that contains 0-2 ppm of S, 0-2 ppm of Ag, 0-1 ppm of Se and 0-1 ppm of Te as incidental impurities with the total content of these and any other incidental impurities present being held at a level not exceeding 10 ppm. By subjecting it to an appropriate heat treatment, the wire acquires an elongation of 5-22%, a breaking strength of 14-33 kg/mm.sup.2, and a Vickers hardness of 38-50, the latter value being measured with respect to said high-purity copper in an ingot form.

Abstract: The present invention eliminates the problems associated with the use of oxygen-free copper and other high-purity copper materials as bonding wires. In accordance with one aspect of the present invention, at least one rare earth element, or at least one element selected from the group consisting of Mg, Ca, Ti, Zr, Hf, Li, Na, K, Rb and Cs, or the combination of at least one rare earth element and at least one elemented selected from the above-specified group is incorporated in high-purity copper as a refining component in an amount of 0.1-100 ppm on a weight basis, and the high-purity copper is subsequently refined by zone melting. The very fine wire drawn from the so refined high-purity copper has the advantage that it can be employed in high-speed ball bonding of a semiconductor chip with a minimum chance of damaging the bonding pad on the chip by the ball forming at the tip of the wire.In accordance with another aspect of the present invention, 0.