Patents by Inventor Toshiaki Sakai

Toshiaki Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030194893
    Abstract: An arc-resistant terminal, couple, and connecter are provided. In an embodiment, a metal-based electrical contact portion thereof includes at least one of Cu, Ni or Sn, and not more than 0.06 mass % P, wherein the arc-resistant terminal capable of suppressing arc discharge wherein a voltage between the arc-resistant terminal and a second terminal immediately after separation thereof is DC36V to 60V and a current between terminals during contact is 6A to 30A. In another embodiment, the an electrical contact portion comprising at least 80 mass % of metal having a boiling point of not less than 1000 degrees centigrade. According to the present invention, since the electrical contact portion or the final contact portion of the terminal includes a specific metal-based material, even when the voltage applied between the terminals is increased and an arc discharge is liable to be generated, the arc discharge can be suppressed.
    Type: Application
    Filed: April 15, 2003
    Publication date: October 16, 2003
    Applicants: Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd., Autonetworks Technologies, Ltd.
    Inventors: Kouji Ota, Hiroki Hirai, Yoshitugu Tsuji, Masahiro Shibata, Atsushi Kimura, Toshiaki Sakai, Satoshi Takano, Masahiko Kanda, Narito Yagi
  • Publication number: 20030041275
    Abstract: The invention relates to semiconductor integrated circuit devices having a circuit operating in synchronism with a clock signal, and it is an object of the invention to provide a semiconductor integrated circuit device in which clock skew between lines that occurs as a result of a change in the circuit layout of the LSI can be easily optimized. There is provided a configuration including an inverter of a clocked circuit formed on a silicon substrate and operating in synchronism with a clock signal, an inverter of a clock timing adjusting circuit formed in an SOI structure, and a via hole for electrically connecting the inverters.
    Type: Application
    Filed: March 19, 2002
    Publication date: February 27, 2003
    Applicant: Fujitsu Limited
    Inventors: Shigeru Nishio, Tsutomu Ohtsu, Tatsuya Fukazawa, Hirokazu Tanaka, Masayasu Hojo, Satoshi Masuda, Yoriko Matuura, Toshiaki Sakai
  • Publication number: 20020187307
    Abstract: A cleaning sheet for printer cylinders is produced by three-dimensionally aggregating fibers into a sheet in a wet paper-making process. The cleaning sheet contains thermofusible fibers that serves as binder fibers, and is creped by heating it at a temperature at which the thermofusible binder fibers therein fuse to thereby make the sheet surface have numerous irregularities.
    Type: Application
    Filed: March 27, 2002
    Publication date: December 12, 2002
    Inventors: Makoto Tanaka, Tadao Mohara, Yoshitsugu Hama, Toshiaki Sakai
  • Publication number: 20020127822
    Abstract: A high-concentration impurity region is formed on all or a part of a surface of an Si forming the third layer, an oxide film (SiO2) forming the second layer is formed on the entire surface of the third layer, the third layer and an Si substrate forming the first layer are bonded together, and the Si forming the third layer is mirror-polished to manufacture an SOI wafer. A resist is then patterned on the SOI wafer, grooves and holes for specifying the contour of the structure are formed in the Si forming the third layer, and the oxide film SiO2 forming the second layer opposed to the formed detecting structure is removed. At the same time, an uneveness of about 0.01 to 0.5 &mgr;m is formed on the surface of the third layer, on which the high-concentration impurity region is formed.
    Type: Application
    Filed: February 25, 2002
    Publication date: September 12, 2002
    Inventors: Katsumichi Ueyanagi, Mitsuo Sasaki, Toshiaki Sakai
  • Patent number: 5503034
    Abstract: A force sensor comprises a substrate having a movable unit which is displaceable in response to one of an applied force and acceleration; an electron emission unit having a cathode for emitting electrons in accordance with an applied potential; an electron absorption unit having an anode for capturing electrons emitted from the cathode, the electron emission unit and the electron absorption unit being formed on a surface of the substrate; and a control unit for, on the basis of the displacement of the movable unit, controlling the electron capturing efficiency of the anode with respect to electrons emitted from the cathode.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: April 2, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Amano, Kazuo Matsuzaki, Toshiaki Sakai
  • Patent number: 5499535
    Abstract: A force sensor comprises a substrate having a movable unit which is displaceable in response to one of an applied force and acceleration; an electron emission unit having a cathode for emitting electrons in accordance with an applied potential; an electron absorption unit having an anode for capturing electrons emitted from the cathode, the electron emission unit and the electron absorption unit being formed on a surface of the substrate; and a control unit for, on the basis of the displacement of the movable unit, controlling the electron capturing efficiency of the anode with respect to electrons emitted from the cathode.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: March 19, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Amano, Kazuo Matsuzaki, Toshiaki Sakai
  • Patent number: 5492011
    Abstract: A force sensor comprises a substrate having a movable unit which is displaceable in response to one of an applied force and acceleration; an electron emission unit having a cathode for emitting electrons in accordance with an applied potential; an electron absorption unit having an anode for capturing electrons emitted from the cathode, the electron emission unit and the electron absorption unit being formed on a surface of the substrate; and a control unit for, on the basis of the displacement of the movable unit, controlling the electron capturing efficiency of the anode with respect to electrons emitted from the cathode.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: February 20, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Amano, Kazuo Matsuzaki, Toshiaki Sakai
  • Patent number: 5463810
    Abstract: A plunger barrel has a sliding bore in which a plunger is slid, a sleeve acceptor in the shape of a hole for a control sleeve which is formed in an intermediate portion of the sliding bore and a window portion which is opened in a wall defining the sleeve acceptor. The plunger barrel is manufactured by the steps of preparing a blank having one end portion and another end portion, forming a first bore axially from the one end portion of the blank, so as to provide a diameter equal to that of the sleeve acceptor, to an intermediate portion of the blank, drawing the one end portion of the blank so that a portion in which the sleeve acceptor is formed remains, forming a second sliding bore in the blank so as to penetrate from the one end portion to the other end portion of the blank, and forming a window portion in a wall of the sleeve acceptor.
    Type: Grant
    Filed: October 25, 1993
    Date of Patent: November 7, 1995
    Assignee: Zexel Corporation
    Inventors: Toshihiro Nakagawa, Toshiaki Sakai, Hiroaki Nozaki
  • Patent number: 5216296
    Abstract: A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: June 1, 1993
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Tsunoi, Kazumasa Nawata, Toshiaki Sakai, Hiroki Yada, Hisayosi Ooba, Takayuki Tsuru, Satoru Sudo, Taichi Saitoh
  • Patent number: 5196638
    Abstract: A muting device of an upright piano which includes butt, a wippen, a capstan button and a muting mechanism (15). This butt rotates with a hammer which strikes a string of the upright piano. In addition, a jack is provided to come in contact with a lower surface of the butt, and rotates the butt in response to displacement of the key. The jack is supported by the wippen such that it can freely rotate. The capstan button is provided at a back edge portion of the key to transmit displacement of the key to the wippen. The muting mechanism is designed to reduce a string-striking stroke by rotating the hammer. Further, there is provided a key-displacement-transmission-rate changing mechanism. When reducing the string-striking stroke by the muting mechanism, this mechanism raises a displacement transmission point, at which displacement of the key is transmitted to the wippen, toward a rotation center of the key from the capstan button.
    Type: Grant
    Filed: June 25, 1991
    Date of Patent: March 23, 1993
    Assignee: Yamaha Corporation
    Inventors: Hajime Hayashida, Satoshi Inoue, Toshiaki Sakai
  • Patent number: 5144158
    Abstract: A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.
    Type: Grant
    Filed: April 17, 1990
    Date of Patent: September 1, 1992
    Assignee: Fujitsu Limited
    Inventors: Yasunori Kanai, Kazumasa Nawata, Mitsuhisa Shimizu, Hiroki Yada, Taichi Saitoh, Toshiaki Sakai
  • Patent number: 5118973
    Abstract: An improved emitter coupled logic circuit suitable for high speed logic operation independent of capacitive load. With previous circuits as the load to be driven become heavier, the capacitive load required a longer time for discharge and the output signal was dulled, resulting in adverse effect on the logic operation when the output changed to a low level from a high level. A pulse has also been previously applied to a pull-down transistor connected between the output and a power source through a capacitor from an inverted phase output to actively discharge the capacitive load. However, when the capacitor is connected to the output it hinders the switching speed of a current switch. In the present invention, a transistor is provided an input circuit and a pulse is applied to a pull-down transistor from the transistor. As a result, an extra capacitive element is not connected to the output end, but a pulse is applied to the pull-down transistor.
    Type: Grant
    Filed: August 22, 1990
    Date of Patent: June 2, 1992
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Sakai, Taichi Saitoh
  • Patent number: 4924742
    Abstract: A mechanical keyboard according to the present invention has a main sostenuto pedal mechanism for holding off a damper associated with a key depressed and an auxiliary sostenuto pedal mechanism provided for keys of a bass range for holding off the associated damper or dampers, and the auxiliary pedal is provided in the vicinity of a soft pedal for easy depression.
    Type: Grant
    Filed: June 6, 1989
    Date of Patent: May 15, 1990
    Assignee: Yamaha Corporation
    Inventors: Motoichi Numata, Kinya Nozaki, Hajime Hayashida, Toshiaki Sakai
  • Patent number: 4918563
    Abstract: A semiconductor device such as an ECL gate array having emitter-follower-type output transistors, wherein protective elements are arranged between input/output pads and a power supply line connected to the collectors of the emitter-follower-type output transistors, whereby wiring between the protective elements and the power supply line become unnecessary so that the manufacturing process becomes easy and the integration degree is improved while a large tolerance voltage is maintained against destruction due to static electricity.
    Type: Grant
    Filed: February 27, 1989
    Date of Patent: April 17, 1990
    Assignee: Fujitsu Limited
    Inventors: Yasunori Kanai, Kazumasa Nawata, Mitsuhisa Shimizu, Toshiaki Sakai
  • Patent number: 4731621
    Abstract: A recording apparatus having a printing head, comprises a support having heating elements, a film being contacted the support to face the elements and having nozzle holes on a region facing the elements, an ink holder, arranged near the holes and on one of opposing surfaces of the film and the support, for holding externally supplied ink, and a vibrator for vibrating the support to supply ink to the holes from the ink holder through a gap between the opposing surfaces of the film and the support.In another embodiment a drive unit may reciprocally move the nozzle member in the alignment direction. In a further embodiment the drive unit may reciprocally move the film and spacer relative to the support and the ink supplier.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: March 15, 1988
    Assignees: Kabushiki Kaisha Toshiba, Soartec Corporation
    Inventors: Mamoru Hayamizu, Ichiro Sano, Toshiaki Sakai
  • Patent number: 4673515
    Abstract: In formation of a fibrous bearing bush for holding center pins on a piano action, synthetic resin of low saturated moisture content or is contained for stabler holding of the center pins under different environmental conditions and presence of lubricative resin on the center pin contact side assures small rolling contact with the center pin.
    Type: Grant
    Filed: September 17, 1985
    Date of Patent: June 16, 1987
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Toshiaki Sakai
  • Patent number: D300876
    Type: Grant
    Filed: September 1, 1987
    Date of Patent: April 25, 1989
    Assignee: Twinbird Industrial Company Limited
    Inventor: Toshiaki Sakai