Patents by Inventor Toshiaki Tsutsumi

Toshiaki Tsutsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9503018
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20160142011
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 19, 2016
    Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
  • Patent number: 9252793
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Patent number: 8968062
    Abstract: A vehicle air conditioner provided with an airflow structure for an intake box, wherein, in an HVAC comprising, in an intake box, a control device for controlling the number of rotation, the control device is reliably cooled by airflow regardless of the ratio of mixing between internal air and external air. A vehicle air conditioner of center-concentrated type, wherein a control device (6) for controlling the number of rotation is mounted to a vehicle interior-side wall surface inside an intake box (2) and wherein an air delivery guide (22) is provided in the intake box (2), the air delivery guide (22) delivering to the control device (6) a part of air introduced from a direction crossing the direction of opening of a suction opening (7) of a blower (8).
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: March 3, 2015
    Assignee: Valeo Thermal Systems Japan Corporation
    Inventors: Toshiaki Tsutsumi, Takayuki Arai, Masayuki Murase, Daisuke Araki
  • Publication number: 20130314165
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 28, 2013
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Patent number: 8338247
    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
  • Patent number: 8148248
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: April 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
  • Patent number: 8022445
    Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
  • Publication number: 20110207317
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Application
    Filed: March 22, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
  • Publication number: 20110171897
    Abstract: A vehicle air conditioner provided with an airflow structure for an intake box, wherein, in an HVAC comprising, in an intake box, a control device for controlling the number of rotation, the control device is reliably cooled by airflow regardless of the ratio of mixing between internal air and external air. A vehicle air conditioner of center-concentrated type, wherein a control device (6) for controlling the number of rotation is mounted to a vehicle interior-side wall surface inside an intake box (2) and wherein an air delivery guide (22) is provided in the intake box (2), the air delivery guide (22) delivering to the control device (6) a part of air introduced from a direction crossing the direction of opening of a suction opening (7) of a blower (8).
    Type: Application
    Filed: August 24, 2009
    Publication date: July 14, 2011
    Applicant: VALEO THERMAL SYSTEMS JAPAN CORPORATION
    Inventors: Toshiaki Tsutsumi, Takayuki Arai, Masayuki Murase, Daisuke Araki
  • Patent number: 7936016
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 3, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Tomonori Okudaira, Keiichiro Kashihara, Tadashi Yamaguchi
  • Publication number: 20110037103
    Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 17, 2011
    Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Kotaro KIHARA
  • Patent number: 7872314
    Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
  • Publication number: 20100230761
    Abstract: To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 16, 2010
    Inventors: Tadashi Yamaguchi, Toshiaki Tsutsumi, Satoshi Ogino, Kazumasa Yonekura, Kenji Kawai, Yoshihiro Miyagawa, Tomonori Okudaira, Keiichiro Kashihara, Kotaro Kihara
  • Publication number: 20100171183
    Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 8, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Tadashi YAMAGUCHI, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
  • Patent number: 7696050
    Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 13, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadashi Yamaguchi, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
  • Publication number: 20090291537
    Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.
    Type: Application
    Filed: July 27, 2009
    Publication date: November 26, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Tomonori OKUDAIRA, Toshiaki TSUTSUMI
  • Publication number: 20090283909
    Abstract: There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
    Type: Application
    Filed: March 30, 2009
    Publication date: November 19, 2009
    Inventors: Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Keiichiro KASHIHARA, Tadashi TAMAGUCHI
  • Publication number: 20090079007
    Abstract: The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a <100> crystal orientation.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 26, 2009
    Inventors: TADASHI YAMAGUCHI, Keiichiro Kashihara, Toshiaki Tsutsumi, Tomonori Okudaira
  • Publication number: 20080272461
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: June 26, 2008
    Publication date: November 6, 2008
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno