Patents by Inventor Toshiaki Yasue

Toshiaki Yasue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7398522
    Abstract: To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency collection portion for collecting loop process frequencies with which the loop process is executed in the program, an in-loop process frequency collection portion for collecting in-loop process frequencies with which, as against times of execution of loop process, each of a plurality of in-loop processes included in the loop process is executed, an in-loop execution information generating portion for generating in-loop execution information indicating the frequencies with which each of the plurality of in-loop processes is executed in the case where the program is executed, and an optimization portion for optimizing the program based on the in-loop execution information.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hideaki Komatsu, Toshio Suganuma, Toshiaki Yasue
  • Publication number: 20080162909
    Abstract: To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency collection portion for collecting loop process frequencies with which the loop process is executed in the program, an in-loop process frequency collection portion for collecting in-loop process frequencies with which, as against times of execution of loop process, each of a plurality of in-loop processes included in the loop process is executed, an in-loop execution information generating portion for generating in-loop execution information indicating the frequencies with which each of the plurality of in-loop processes is executed in the case where the program is executed, and an optimization portion for optimizing the program based on the in-loop execution information.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 3, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hideaki Komatsu, Toshio Suganuma, Toshiaki Yasue
  • Patent number: 7383417
    Abstract: The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a plurality of data readings issued by the program while performing data reading; a prefetching generator, for generating a plurality of prefetchings that correspond to the plurality of data readings recorded in the history; a prefetching process determination unit, for determining, based on the history, the performance order for the plurality of prefetchings; and a prefetching unit, for performing, when following the determination of the performance order the program is executed, the plurality of prefetchings in the performance order.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Yasue, Hideaki Komatsu
  • Publication number: 20070277166
    Abstract: A system and method are provided that in one aspect eliminate redundant array range checks by performing a versioning for a loop. In another aspect, a system and method optimize array range checks by performing data-flow analysis in reverse order of the program execution. Yet in another aspect, a system and method obtains information about array ranges already checked by performing data-flow analysis in program execution order and eliminate redundant array range checks from this information.
    Type: Application
    Filed: August 14, 2007
    Publication date: November 29, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshiaki Yasue, Hideaki Komatsu
  • Patent number: 7260817
    Abstract: A system and method are provided that in one aspect eliminate redundant array range checks by performing a versioning for a loop. In another aspect, a system and method optimize array range checks by performing data-flow analysis in reverse order of the program execution. Yet in another aspect, a system and method obtains information about array ranges already checked by performing data-flow analysis in program execution order and eliminate redundant array range checks from this information.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: August 21, 2007
    Assignee: International Business Machines Corporation
    Inventors: Motohiro Kawahito, Toshiaki Yasue, Hideaki Komatsu
  • Publication number: 20070005905
    Abstract: The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a plurality of data readings issued by the program while performing data reading; a prefetching generator, for generating a plurality of prefetchings that correspond to the plurality of data readings recorded in the history; a prefetching process determination unit, for determining, based on the history, the performance order for the plurality of prefetchings; and a prefetching unit, for performing, when following the determination of the performance order the program is executed, the plurality of prefetchings in the performance order.
    Type: Application
    Filed: March 15, 2006
    Publication date: January 4, 2007
    Inventors: Toshiaki Yasue, Hideaki Komatsu
  • Publication number: 20040261067
    Abstract: To collect frequencies with which processes of a program are executed at high speed. A compiler apparatus for optimizing a program based on frequencies with which each process is executed has a loop process detection portion for detecting a repeatedly executed loop process of the program, a loop process frequency collection portion for collecting loop process frequencies with which the loop process is executed in the program, an in-loop process frequency collection portion for collecting in-loop process frequencies with which, as against times of execution of loop process, each of a plurality of in-loop processes included in the loop process is executed, an in-loop execution information generating portion for generating in-loop execution information indicating the frequencies with which each of the plurality of in-loop processes is executed in the case where the program is executed, and an optimization portion for optimizing the program based on the in-loop execution information.
    Type: Application
    Filed: March 10, 2004
    Publication date: December 23, 2004
    Applicant: International Business Machines Corporation
    Inventors: Hideaki Komatsu, Toshio Suganuma, Toshiaki Yasue
  • Patent number: 6665864
    Abstract: The present invention eliminates redundant array range checks. A two-phased check is performed, namely a wide range check is performed by combining a plurality of array range checks, and a strict range check is unsuccessful, so as to reduce the number of range checks at execution time and allow execution at high speed. For instance, it is possible with a processor such as PowerPC, by using a flag, to invalidate a code for performing an array range check at high speed without increasing a code size. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed. Also, for instance, a plurality of array range checks can be combined without considering existence of instructions which cause a side effect. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Motohiro Kawahito, Hideaki Komatsu, Toshiaki Yasue
  • Publication number: 20030204839
    Abstract: Java language is, as its specification, capable of detecting an access exceeding an array range, and when there is no user-defined exception handler, moving control to an invoked method after getting out of a method in which an exception occurred, or when there is a user-defined exception handler, moving the process to the exception handler. Accordingly, an array range check is essential since occurrence of an exception may be described as a correct operation. However, an array range check slows execution speed compared with a language which does not require it. In an actual program, there is an array access to ensure that there is no access exceeding a range, and thus elimination of such redundant range checks greatly contributes to improved performance, and in addition, brings about an effect of expanding the range of optimization from the viewpoint of ensuring order of execution between occurrence of an exception and a process with a side effect such as an assignment of a value to an array.
    Type: Application
    Filed: December 30, 2002
    Publication date: October 30, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshiaki Yasue, Hideaki Komatsu
  • Patent number: 6519765
    Abstract: Java language is, as its specification, capable of detecting an access exceeding an array range, and when there is no user-defined exception handler, moving control to an invoked method after getting out of a method in which an exception occurred, or when there is a user-defined exception handler, moving the process to the exception handler. Accordingly, an array range check is essential since occurrence of an exception may be described as a correct operation. However, an array range check slows execution speed compared with a language which does not require it. In an actual program, there is an array access to ensure that there is no access exceeding a range, and thus elimination of such redundant range checks greatly contributes to improved performance, and in addition, brings about an effect of expanding the range of optimization from the viewpoint of ensuring order of execution between occurrence of an exception and a process with a side effect such as an assignment of a value to an array.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Motohiro Kawahito, Toshiaki Yasue, Hideaki Komatsu
  • Patent number: 6363521
    Abstract: The present invention is directed to expanding the scope of execution optimization by method inlining in a language with a security facility such as Java. More particularly, the present invention is directed to a step of generating a code necessary for looping by a tail recursion for a first method including an invocation of a method whose process after its invocation is indefinite and which includes a self recursion, and a step of generating a code for counting the number of iterations of the loop are included. SecurityManager corrects the depth of the frame associated with a second method in the storage area by using the count value by the code for counting the number of iterations of the loop.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: March 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Yasue, Hideaki Komatsu, Takeshi Ogasawara