Abstract: A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal.

Abstract: A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal.

Abstract: A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other and a control circuit, wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and when the control signal has a second value, the control circuit supplies no current to the PMOS transistors and selectively turns on one of the NMOS transistors, thereby controlling the output driving circuits to output a second pair of differential signals.

Abstract: A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other and a control circuit, wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and when the control signal has a second value, the control circuit supplies no current to the PMOS transistors and selectively turns on one of the NMOS transistors, thereby controlling the output driving circuits to output a second pair of differential signals.