Abstract: When a music file is played back as a piece of music, a CPU obtains date and time information associated with a music file to be played back, searches among image files memorized in a memory for an image file with which date and time information corresponding to the date and time information is associated, and causes a display unit to play back the searched image file while the music file is being played back. In addition, when an image file is played back as an image, the CPU searches among music files memorized in the memory for a music file with which date and time information corresponding to date and time information associated with an image Pile to be played back is associated, and causes a speaker to play back the searched music file while the image file is being played back.

Abstract: A clock signal generating circuit is disclosed. The clock signal generating circuit includes: a reference clock signal generating unit for generating a reference clock signal; a plurality of frequency dividing units for carrying out frequency dividing of the reference clock signal and outputting frequency-divided clock signals; a plurality of frequency division ratio storing units for storing frequency division ratios different from each other for the respective frequency dividing units; and a switching unit for switching, synchronously with the reference clock signal, at least one initial frequency division ratio at the frequency dividing units to the frequency division ratios stored in the corresponding frequency division ratio storing units.

Abstract: A clock signal generating circuit is disclosed. The clock signal generating circuit includes: a reference clock signal generating unit for generating a reference clock signal; a plurality of frequency dividing units for carrying out frequency dividing of the reference clock signal and outputting frequency-divided clock signals; a plurality of frequency division ratio storing units for storing frequency division ratios different from each other for the respective frequency dividing units; and a switching unit for switching, synchronously with the reference clock signal, at least one initial frequency division ratio at the frequency dividing units to the frequency division ratios stored in the corresponding frequency division ratio storing units.

Abstract: A video receiving tuner relating to the present invention comprises an input terminal for receiving video reception signals that are digitally modulated, a front-end block for amplifying the video reception signals fed thereto from the input terminal and selecting a signal of one channel as a selection signal from among the amplified video reception signals, a digital demodulation circuit block for demodulating the selection signal into a digital signal, a re-modulation circuit block for modulating a carrier wave having a predetermined frequency by the digital signal so as to produce a re-modulation signal, a transmission circuit block for processing the re-modulation signal fed thereto from the re-modulation circuit and outputting a resultant signal as a radio signal, an antenna for transmitting the radio signal, and a casing for enclosing the front-end block, the digital demodulation circuit block, the re-modulation circuit block, and the transmission circuit block.

Abstract: The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.

Abstract: The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.

Abstract: The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.

Abstract: The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.