Abstract: A power supply unit is arranged between a CPU and a power supply device for supplying power to the CPU. Information necessary in proceeding with a program is evacuated from the CPU to an information holding unit. When a power shutdown factor is generated, a power supply control unit outputs a shutdown request signal to the CPU. The CPU, upon receiving the shutdown request signal, activates a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after the evacuation is completed. Upon receiving the evacuation completed signal, the power supply control unit outputs a power shutdown control signal to the power supply unit. Upon receiving the power shutdown control signal from the power supply control unit, the power supply unit shuts down power supply to the CPU.

Abstract: A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.

Abstract: An information apparatus comprises: a barrel shifter composed of a bidirectional 1-bit shifter, . . . , and a bidirectional 24-bit shifter which are connected in series; a control unit for outputting an endian conversion control signal SE indicating one of a shift operation and endian conversion; an endian conversion unit for generating data by endian conversion using data obtained by performing a shift operation in the bidirectional 8-bit shifter and the bidirectional 24-bit shifter; and a selector for selecting, when the endian conversion control signal SE indicates a shift operation, data outputted from the bidirectional 24-bit shifter, and selecting, when the endian conversion control signal SE indicates endian conversion, the data outputted from the endian conversion unit.

Abstract: A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the plurality of debug modes, and is allowed to shift to the interruption program during the debugging operation in another debug mode.

Abstract: A power supply unit is arranged between a CPU and a power supply device for supplying power to the CPU. Information necessary in proceeding with a program is evacuated from the CPU to an information holding unit. When a power shutdown factor is generated, a power supply control unit outputs a shutdown request signal to the CPU. The CPU, upon receiving the shutdown request signal, activates a power shutdown microprogram, evacuates the information necessary in proceeding with the program to the information holding unit, and outputs an evacuation completed signal to the power supply control unit after the evacuation is completed. Upon receiving the evacuation completed signal, the power supply control unit outputs a power shutdown control signal to the power supply unit. Upon receiving the power shutdown control signal from the power supply control unit, the power supply unit shuts down power supply to the CPU.

Abstract: A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.

Abstract: A first comparator outputs a first signal indicative that a voltage determined according to the amount of charge stored in a first capacitor has reached a first reference voltage. A second comparator outputs a second signal indicative that a voltage determined according to the amount of charge stored in a second capacitor has reached a second reference voltage. An RS flip flop circuit is shifted to a set state by one of the first signal and the second signal and shifted to a reset state by the other signal. When the RS flip flop circuit is in the set state, the first capacitor is in a charge state, and the second capacitor is in a discharge state. When the RS flip flop circuit is in the reset state, the first capacitor is in a discharge state, and the second capacitor is in a charge state.

Abstract: In a microprocessor that interprets instructions where a same instruction code can be interpreted as separate instructions with respectively different data lengths, a data length storage circuit that stores data length selection-use information is provided in a decoding unit. Instructions instructing storage to a general-purpose register, such storage of 8-bit immediate data to register R1, are set in advance as first-type instructions. Instructions that do not explicitly specify a data length, in other words, instructions whose processing targets are various lengths of data stored in the general-purpose register are set in advance as second-type instructions. When decoding a first-type instruction, the decoding unit updates the data length selection-use information in accordance with the first-type instruction.

Abstract: An oscillator circuit and an oscillation stabilizing method are provided that can improve the productivity of products, stabilize an oscillating operation, and achieve more stable operations for a system supplied with oscillation output. An output from a variable capability oscillator circuit is received by two inverters having different threshold values. Regarding voltage values that are exceeded when oscillation is stabilized in the inverters, the boundaries of the voltage values are set as an astable boundary and an astable boundary which are the threshold values of the inverters, outputs from the inverters are counted by a stable oscillation period shortening circuit based on the timing of a clock used for the system, and the capability of the variable capability oscillator circuit is maximized until oscillation is stabilized, thereby further shortening a stable oscillation period.

Abstract: An oscillator circuit and an oscillation stabilizing method are provided that can improve the productivity of products, stabilize an oscillating operation, and achieve more stable operations for a system supplied with oscillation output. An output from a variable capability oscillator circuit is received by two inverters having different threshold values. Regarding voltage values that are exceeded when oscillation is stabilized in the inverters, the boundaries of the voltage values are set as an astable boundary and an astable boundary which are the threshold values of the inverters, outputs from the inverters are counted by a stable oscillation period shortening circuit based on the timing of a clock used for the system, and the capability of the variable capability oscillator circuit is maximized until oscillation is stabilized, thereby further shortening a stable oscillation period.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.

Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.