Patents by Inventor Toshifumi Irisawa
Toshifumi Irisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10636751Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.Type: GrantFiled: August 3, 2016Date of Patent: April 28, 2020Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGYInventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
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Publication number: 20190019766Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.Type: ApplicationFiled: August 3, 2016Publication date: January 17, 2019Inventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
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Patent number: 9780170Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.Type: GrantFiled: July 7, 2016Date of Patent: October 3, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensuke Ota, Toshifumi Irisawa, Tomoya Kawai, Daisuke Matsushita, Tsutomu Tezuka
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Patent number: 9614103Abstract: A semiconductor device according to an embodiment includes a first region including an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), a second region and a third region between which the first region is disposed, at least one of the second region and the third region having a higher indium (In) concentration than the first region and containing at least one metal element from the group consisting of titanium (Ti), tungsten (W), copper (Cu), zinc (Zn), aluminum (Al), lead (Pb), and tin (Sn), an electrode; and an insulating layer disposed between the first region and the electrode.Type: GrantFiled: January 20, 2016Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Ota, Toshifumi Irisawa, Masumi Saitoh, Kiwamu Sakuma
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Publication number: 20170040416Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.Type: ApplicationFiled: July 7, 2016Publication date: February 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke OTA, Toshifumi IRISAWA, Tomoya KAWAI, Daisuke MATSUSHITA, Tsutomu TEZUKA
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Publication number: 20160218224Abstract: A semiconductor device according to an embodiment includes a first region including an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), a second region and a third region between which the first region is disposed, at least one of the second region and the third region having a higher indium (In) concentration than the first region and containing at least one metal element from the group consisting of titanium (Ti), tungsten (W), copper (Cu), zinc (Zn), aluminum (Al), lead (Pb), and tin (Sn), an electrode; and an insulating layer disposed between the first region and the electrode.Type: ApplicationFiled: January 20, 2016Publication date: July 28, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kensuke Ota, Toshifumi Irisawa, Masumi Saitoh, Kiwamu Sakuma
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Patent number: 8778766Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: GrantFiled: September 14, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Toshifumi Irisawa
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Publication number: 20130005106Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu TEZUKA, Toshifumi IRISAWA
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Patent number: 8288760Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: GrantFiled: May 10, 2010Date of Patent: October 16, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Toshifumi Irisawa
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Publication number: 20120241722Abstract: A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.Type: ApplicationFiled: September 22, 2011Publication date: September 27, 2012Inventors: Keiji Ikeda, Toshifumi Irisawa, Toshinori Numata, Tsutomu Tezuka
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Patent number: 8174095Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: GrantFiled: February 28, 2011Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
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Patent number: 8008751Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: GrantFiled: December 5, 2007Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
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Publication number: 20110147805Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
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Publication number: 20100219480Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: ApplicationFiled: May 10, 2010Publication date: September 2, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Toshifumi Irisawa
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Patent number: 7728324Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: GrantFiled: March 20, 2007Date of Patent: June 1, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Toshifumi Irisawa
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Patent number: 7622773Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.Type: GrantFiled: February 13, 2007Date of Patent: November 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Irisawa, Toshinori Numata, Shinichi Takagi, Naoharu Sugiyama
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Patent number: 7619239Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.Type: GrantFiled: May 22, 2006Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Irisawa, Toshinori Numata, Tsutomu Tezuka, Naoharu Sugiyama, Shinichi Takagi
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Patent number: 7514753Abstract: A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si1-a Gea (0?a?1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si1-c Gec (0?c?1, a?c).Type: GrantFiled: June 11, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Toshifumi Irisawa, Atsuhiro Kinoshita, Junji Koga
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Publication number: 20080135886Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: ApplicationFiled: December 5, 2007Publication date: June 12, 2008Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
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Publication number: 20080001171Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.Type: ApplicationFiled: March 20, 2007Publication date: January 3, 2008Inventors: Tsutomu Tezuka, Toshifumi Irisawa