Patents by Inventor Toshifumi Ishimori
Toshifumi Ishimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11695404Abstract: According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.Type: GrantFiled: September 14, 2021Date of Patent: July 4, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Kentaro Arai, Toshifumi Ishimori, Yutaka Yadoumaru, Masayoshi Takahashi
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Publication number: 20220311430Abstract: According to one embodiment, a semiconductor device includes a first circuit, a first terminal, a second terminal, a conductor and a first switch element serially coupled between the first terminal and the second terminal, wherein the first circuit is configured to turn the first switch element to an OFF state when a first condition is satisfied, and the conductor is configured to physically break when a second condition is satisfied.Type: ApplicationFiled: September 14, 2021Publication date: September 29, 2022Inventors: Kentaro ARAI, Toshifumi ISHIMORI, Yutaka YADOUMARU, Masayoshi TAKAHASHI
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Patent number: 11437965Abstract: A variable gain amplifier according to an embodiment comprises a first path, a matching circuit, an amplifier circuit, a second path, and a third path. The first path includes an attenuation circuit, has one end connected to a first input terminal, and attenuates an input signal and outputs an attenuated signal. The matching circuit has one end connected to the other end of the first path. The amplifier circuit has an input connected to the other end of the matching circuit and an output connected to a first output terminal, and amplifies an input signal. The second path is connected in parallel to the first path. The third path has one end connected to the first input terminal, and the other end connected to the first output terminal.Type: GrantFiled: September 11, 2020Date of Patent: September 6, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Shinji Ohno, Toshifumi Ishimori
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Publication number: 20210297049Abstract: A variable gain amplifier according to an embodiment comprises a first path, a matching circuit, an amplifier circuit, a second path, and a third path. The first path includes an attenuation circuit, has one end connected to a first input terminal, and attenuates an input signal and outputs an attenuated signal. The matching circuit has one end connected to the other end of the first path. The amplifier circuit has an input connected to the other end of the matching circuit and an output connected to a first output terminal, and amplifies an input signal. The second path is connected in parallel to the first path. The third path has one end connected to the first input terminal, and the other end connected to the first output terminal.Type: ApplicationFiled: September 11, 2020Publication date: September 23, 2021Inventors: Shinji OHNO, Toshifumi Ishimori
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Patent number: 10778221Abstract: According to one embodiment, a first switch controls conduction between first and second nodes according to a potential on a first control node. A second switch controls conduction between the first control node and a first potential node according to a potential on a second control node. A first circuit includes first and second output nodes respectively coupled to the first and second control nodes, and outputs at the second output node a potential that brings the second switch out of conduction while outputting a first potential at the first output node. The first circuit has a high impedance at the first output node while outputting at the second output node a potential that brings the second switch into conduction.Type: GrantFiled: June 6, 2019Date of Patent: September 15, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronics Devices & Storage CorporationInventors: Shinji Ohno, Toshifumi Ishimori, Mitsuru Sugawara
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Publication number: 20200228117Abstract: According to one embodiment, a first switch controls conduction between first and second nodes according to a potential on a first control node. A second switch controls conduction between the first control node and a first potential node according to a potential on a second control node. A first circuit includes first and second output nodes respectively coupled to the first and second control nodes, and outputs at the second output node a potential that brings the second switch out of conduction while outputting a first potential at the first output node. The first circuit has a high impedance at the first output node while outputting at the second output node a potential that brings the second switch into conduction.Type: ApplicationFiled: June 6, 2019Publication date: July 16, 2020Inventors: Shinji Ohno, Toshifumi Ishimori, Mitsuru Sugawara
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Patent number: 9595945Abstract: A switch control circuit includes a plurality of first voltage generation circuits that generate a plurality of second control signals by level-shifting a plurality of first control signals using a reference voltage. A plurality of cut-off circuits controlling whether or not to supply the reference voltage to a corresponding one of the plurality of first voltage generation circuits. A control circuit is configured to control the cut-off circuits in such a manner that the reference voltage supplied to at least one first voltage generation circuit is cut off to the other first voltage generation circuits after a state of the first control signal supplied to the at least one first generation circuit is changed. In some embodiments, the reference voltage to the other first generation circuits is cut-off for a predetermined time period.Type: GrantFiled: February 29, 2016Date of Patent: March 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yugo Kunishi, Toshifumi Ishimori, Toshiki Seshita
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Publication number: 20160269003Abstract: A switch control circuit includes a plurality of first voltage generation circuits that generate a plurality of second control signals by level-shifting a plurality of first control signals using a reference voltage. A plurality of cut-off circuits controlling whether or not to supply the reference voltage to a corresponding one of the plurality of first voltage generation circuits. A control circuit is configured to control the cut-off circuits in such a manner that the reference voltage supplied to at least one first voltage generation circuit is cut off to the other first voltage generation circuits after a state of the first control signal supplied to the at least one first generation circuit is changed. In some embodiments, the reference voltage to the other first generation circuits is cut-off for a predetermined time period.Type: ApplicationFiled: February 29, 2016Publication date: September 15, 2016Inventors: Yugo KUNISHI, Toshifumi ISHIMORI, Toshiki SESHITA
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Patent number: 8686708Abstract: A switching circuit includes: a switching section including at least one first terminal, a plurality of second terminals, and a switching element configured to connect the first terminal to one of the second terminals; a driver driving the switching element in accordance with an external terminal switching control signal; a DC-to-DC converter, which supplies electric power to the driver, having a first state with a response to a load transient and a second state with the response to a load transient being slower than the first state; and a power controller controlling the DC-to-DC converter to operate with the first state during a first time period corresponding to change in the external terminal switching control signal, and to operate with the second state during a second time period other than the first time period.Type: GrantFiled: March 16, 2010Date of Patent: April 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Ishimori, Mitsuru Sugawara, Toshiki Seshita
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Patent number: 8391805Abstract: According to one embodiment, a semiconductor switch circuit includes a switch section, a decoder section, a DC-DC converter, a driver section, a first filter circuit, a first filter bypass circuit and a first bypass control circuit. The switch section includes an input-output terminal, radio frequency signal terminals, and semiconductor switch elements. The decoder section generates a switch control signal controlling a conduction and a non-conduction state of switch elements. The DC-DC converter generates a first potential. The driver section supplies the first and a second potential to a gate electrode of the switch elements. The first filter circuit is electrically connected between the DC-DC converter and the driver section and outputs the first potential to the driver section. The first filter bypass circuit is electrically connected with the first filter circuit. The first bypass control circuit supplies a first mode signal to the first filter bypass circuit.Type: GrantFiled: March 21, 2011Date of Patent: March 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Ishimori, Toshiki Seshita, Mitsuru Sugawara
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Publication number: 20130005279Abstract: According to one embodiment, a semiconductor switch includes a switch section, a driver, and a power supply. The switch section switches a connection between a common terminal and a plurality of radio-frequency terminals. The driver outputs a control signal to the switch section based on a terminal switching signal. The power supply generates a first potential based on a reference potential varying in accordance with temperature and outputs the first potential to the driver.Type: ApplicationFiled: March 16, 2012Publication date: January 3, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshifumi ISHIMORI, Toshiki Seshita
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Publication number: 20120049938Abstract: According to one embodiment, a semiconductor switch circuit includes a switch section, a decoder section, a DC-DC converter, a driver section, a first filter circuit, a first filter bypass circuit and a first bypass control circuit. The switch section includes an input-output terminal, radio frequency signal terminals, and semiconductor switch elements. The decoder section generates a switch control signal controlling a conduction and a non-conduction state of switch elements. The DC-DC converter generates a first potential. The driver section supplies the first and a second potential to a gate electrode of the switch elements. The first filter circuit is electrically connected between the DC-DC converter and the driver section and outputs the first potential to the driver section. The first filter bypass circuit is electrically connected with the first filter circuit. The first bypass control circuit supplies a first mode signal to the first filter bypass circuit.Type: ApplicationFiled: March 21, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshifumi Ishimori, Toshiki Seshita, Mitsuru Sugawara
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Publication number: 20100237842Abstract: A switching circuit includes: a switching section including at least one first terminal, a plurality of second terminals, and a switching element configured to connect the first terminal to one of the second terminals; a driver driving the switching element in accordance with an external terminal switching control signal; a DC-to-DC converter, which supplies electric power to the driver, having a first state with a response to a load transient and a second state with the response to a load transient being slower than the first state; and a power controller controlling the DC-to-DC converter to operate with the first state during a first time period corresponding to change in the external terminal switching control signal, and to operate with the second state during a second time period other than the first time period.Type: ApplicationFiled: March 16, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshifumi Ishimori, Mitsuru Sugawara, Toshiki Seshita