Patents by Inventor Toshifumi KOBE

Toshifumi KOBE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456378
    Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 27, 2022
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Toshiyuki Orita, Tomomi Yamanobe, Makoto Higashihira, Yuuki Doi, Toshifumi Kobe, Masao Tsujimoto, Takao Kaji, Kiyofumi Kondou
  • Publication number: 20220302046
    Abstract: There is provided a semiconductor device including: a circuit region formed on one surface of a semiconductor substrate; a connection portion disposed at the one surface, the connection portion covering the circuit region, being electrically connected to the circuit region, and being used to connect with an exterior device; an annular wire formed at the one surface so as to surround the circuit region; a first protective film covering the annular wire, the first protective film being formed between the connection portion and a peripheral edge portion of the semiconductor substrate; and a second protective film formed at a predetermined partial region on the connection portion.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 22, 2022
    Inventors: KIYOFUMI KONDO, MAMORU ISHIKIRIYAMA, TAKUMI INOUE, KAZUTAKA KODAMA, TOSHIFUMI KOBE, YUZO YAMAMOTO, TOSHIYUKI ORITA, MAKOTO HIGASHIHIRA
  • Patent number: 10964780
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Publication number: 20200035783
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 30, 2020
    Applicant: LAPIS SEMICONDUCTOR CO., LTD
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Publication number: 20190189800
    Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Toshiyuki Orita, Tomomi Yamanobe, Makoto Higashihira, Yuuki Doi, Toshifumi Kobe, Masao Tsujimoto, Takao Kaji, Kiyofumi Kondou
  • Publication number: 20120119371
    Abstract: There is provided a method of fabricating a semiconductor device including: forming an insulating film on a semiconductor substrate; forming a pad electrode on the insulating film; forming a protective film on the pad electrode; forming, on the protective film, a resist equipped with an open portion in a first region corresponding to part of the pad electrode; by using the resist as a mask, etching the protective film and etching the first region of part of the pad electrode to a predetermined depth; etching the protective film on a second region that surrounds the first region of the pad electrode; and removing the resist.
    Type: Application
    Filed: October 13, 2011
    Publication date: May 17, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Yasuhiro MATSUMOTO, Hiroki KUROKI, Toshifumi KOBE, Kiyohiko YOSHINO