Patents by Inventor Toshifumi Morita
Toshifumi Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7781339Abstract: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 ?m or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.Type: GrantFiled: June 19, 2007Date of Patent: August 24, 2010Assignee: Kobe Steel, Ltd.Inventors: Takashi Onishi, Mikako Takeda, Masao Mizuno, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Patent number: 7538027Abstract: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 ?m, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C.Type: GrantFiled: September 18, 2006Date of Patent: May 26, 2009Assignee: Kobe Steel, Ltd.Inventors: Takashi Onishi, Masao Mizuno, Mikako Takeda, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20080014743Abstract: A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 ?m or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.Type: ApplicationFiled: June 19, 2007Publication date: January 17, 2008Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Takashi Onishi, Mikako Takeda, Masao Mizuno, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20070218690Abstract: There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 ?m, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C.Type: ApplicationFiled: September 18, 2006Publication date: September 20, 2007Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)Inventors: Takashi Onishi, Masao Mizuno, Mikako Takeda, Susumu Tsukimoto, Tatsuya Kabe, Toshifumi Morita, Miki Moriyama, Kazuhiro Ito, Masanori Murakami
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Publication number: 20050029011Abstract: A circuit board including a plurality of substrates fixed on a main substrate with solder, wherein the plurality of substrates include a substrate having a smaller thermal expansion coefficient than the main substrate, and wherein the plurality of substrates are made by bonding together a ceramic substrate and a substrate having a higher strength than the ceramic substrate, with the higher-strength substrate bonded to the main substrate side of the ceramic substrate. Since a substrate having a higher strength than a ceramic substrate is bonded to the main substrate side of the ceramic substrate, it is possible to reduce the thermal stress applied to the ceramic substrate side of the circuit board so as to prevent cracking in the ceramic substrate, thus improving the reliability of the circuit board against a thermal stress.Type: ApplicationFiled: August 3, 2004Publication date: February 10, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshifumi Morita, Shigetoshi Segawa
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Patent number: 4389548Abstract: In an acoustic transducer comprising a piezoelectric element for driving a speaker diaphragm, there is provided a cushioning member between a frame body and the piezoelectric element wherein said cushioning member is preliminarily adhered onto the top face of a bottom portion of the frame body by means of an adhering layer formed on the bottom face of the cushioning member with the piezoelectric element preliminarily adhered on the top face of the cushioning member by means of an adhering layer formed on the top face of the cushioning member so as to facilitate to mount the piezoelectric element and a speaker diaphragm on the frame body.Type: GrantFiled: March 27, 1981Date of Patent: June 21, 1983Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Morikawa, Toshifumi Morita, Masayuki Hirate