Patents by Inventor Toshifumi Suganaga
Toshifumi Suganaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10418327Abstract: An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.Type: GrantFiled: December 13, 2017Date of Patent: September 17, 2019Assignee: Renesas Electronics CorporationInventor: Toshifumi Suganaga
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Publication number: 20180233402Abstract: An object of the present invention is to improve the operating characteristics of a semiconductor device. A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.Type: ApplicationFiled: December 13, 2017Publication date: August 16, 2018Inventor: Toshifumi SUGANAGA
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Patent number: 9711344Abstract: To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.Type: GrantFiled: February 4, 2016Date of Patent: July 18, 2017Assignee: Renesas Electronics CorporationInventor: Toshifumi Suganaga
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Publication number: 20160247684Abstract: To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.Type: ApplicationFiled: February 4, 2016Publication date: August 25, 2016Applicant: Renesas Electronics CorporationInventor: Toshifumi SUGANAGA
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Publication number: 20100203456Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.Type: ApplicationFiled: April 26, 2010Publication date: August 12, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
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Patent number: 7727709Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.Type: GrantFiled: January 31, 2007Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
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Publication number: 20070224546Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.Type: ApplicationFiled: January 31, 2007Publication date: September 27, 2007Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
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Patent number: 6717652Abstract: An exposure apparatus and an exposure method according to the present invention comprise an average illuminance operation unit for averaging illuminance values obtained from four illuminance meters provided on a stage and obtaining average illuminance and a light exposure control unit controlling a light exposure on the basis of information obtained from the average illuminance operation unit. Thus, an exposure apparatus and an exposure method capable of correctly managing the light exposure can be provided.Type: GrantFiled: March 30, 2001Date of Patent: April 6, 2004Assignee: Renesas Technology Corp.Inventor: Toshifumi Suganaga
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Publication number: 20020072000Abstract: An exposure apparatus and an exposure method according to the present invention comprise an average illuminance operation unit for averaging illuminance values obtained from four illuminance meters provided on a stage and obtaining average illuminance and a light exposure control unit controlling a light exposure on the basis of information obtained from the average illuminance operation unit. Thus, an exposure apparatus and an exposure method capable of correctly managing the light exposure can be provided.Type: ApplicationFiled: March 30, 2001Publication date: June 13, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Toshifumi Suganaga
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Reticle for use in exposing semiconductor, method of producing the reticle, and semiconductor device
Patent number: 6352800Abstract: A reticle for use in exposing a semiconductor capable of increasing the contrast of a resist pattern to be formed on a wafer through exposure without involvement of a change in the geometry of a diaphragm plate even when a circuit pattern formed on a reticle becomes more minute; a method of producing the reticle; and a semiconductor device. The irregularities 11 are formed in the glass surface 12 of the halftone reticle 10, thus enabling uniform diffusion of the illumination light 15 over the glass surface 12. Consequently, the oblique incident light 20 effective for improving the contrast of an image to be formed on the wafer 112 can be readily and inexpensively increased without involvement of complicated processes. Even when the hole pattern 14 becomes minute, the contrast of a resist pattern to be radiated on the wafer 112 can be improved.Type: GrantFiled: April 14, 2000Date of Patent: March 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshifumi Suganaga -
Patent number: 6295629Abstract: Disclosed herein is how to obtain the magnitude of focus deviation and the direction of the deviation directly from a focus measuring mark. The magnitude of focus deviation is measured from the length of the focus measuring mark (3) in the elongate direction. The length of a tapered part (20) of the focus measuring mark (3) in which the resist gradually becomes thinner is measured from the secondary electron signal waveform of a scanning electron microscope. The direction of the focus deviation is obtained from the measured length of the tapered part (20).Type: GrantFiled: March 12, 1999Date of Patent: September 25, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshifumi Suganaga
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Patent number: 6087693Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.Type: GrantFiled: October 17, 1997Date of Patent: July 11, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshifumi Suganaga, Eiichi Ishikawa
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Patent number: 5776825Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.Type: GrantFiled: June 5, 1997Date of Patent: July 7, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshifumi Suganaga, Eiichi Ishikawa
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Patent number: 5539231Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.Type: GrantFiled: March 2, 1995Date of Patent: July 23, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshifumi Suganaga, Eiichi Ishikawa