Patents by Inventor Toshifumi Yamauchi

Toshifumi Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5177793
    Abstract: On recognizing first through P-th input patterns as first through P-th recognized patterns (P being greater than one) by using a plurality of reference patterns and a plurality of memorized indentifiers identifying the reference patterns, a processing circuit processes the first through the P-th input patterns into first through Q-th provisional patterns different from one another, where Q is not greater than the above-mentioned plurality. A calculating circuit calculates dissimilarity degrees had by the reference patterns relative to the first through the Q-th provisional patterns to select, with repetition allowed as selected patterns, the reference patterns which have the dissimilarity degrees less than a predetermined degree. The calculating circuit thereby selects R particular identifiers and S different identifiers from the memorized identifiers, where R plus S is not greater than P and is not less than the plurality.
    Type: Grant
    Filed: September 20, 1990
    Date of Patent: January 5, 1993
    Assignee: NEC Corporation
    Inventors: Yasumasa Murai, Toshifumi Yamauchi