Abstract: A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.

Abstract: A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.

Abstract: A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.

Abstract: A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.

Abstract: A method of designing a semiconductor integrated circuit is based on a TPI (Test Point Insertion) technique. The design method includes: inserting a test point into a target node in a designed circuit and designating delay time for a test point path connected to the test point. Thereafter, a layout of a designed circuit is made so that delay time of the test point path becomes the above described designated delay time.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.

Abstract: The design for testability method of this invention forms scan paths in a circuit preliminarily-designed with required elements. According to this design method, a plurality of appropriated paths that can be appropriated as scan paths are extracted from the multiplicity of path of the circuit, occupied areas are individually calculated for each of the plurality of appropriated paths both for cases in which scan paths are formed using multiplexers and for cases in which registers are replaced by scan elements, and in each case the scan path having the smaller occupied area is selected and formed. The two types of methods for forming scan paths are selected for each portion of the circuit, thereby allowing scan paths to be formed with the smallest occupied area in the circuit.

Abstract: A logic synthesis for testability system including a testability improving unit which employs a center state of an FSM of a circuit as a target for logic synthesis to reduce a distance between predetermined states for improving testability of the circuit expressed by the FSM which is held in a storage unit, the testability improving unit including a center state candidate selecting unit for excluding an asynchronous reset state and a predetermined state with a short distance from the asynchronous reset state from center state candidates and a center state selecting unit for sequentially selecting states not excluded by the center state candidate selecting unit as center state candidates, thereby conducting optimization processing taking testability into consideration during logic circuit designing.

Abstract: In a logic synthesis-for-testability system including a memory unit (101) for memorizing, as an objective circuit description which is logically synthesized, an FSM (finite state machine) description having a plurality of states, a testability improving unit (106) includes a candidate selecting unit (111) for selecting candidate states among the plurality of states with an asynchronous reset state of the plurality of states excluded from the candidate states. The testability improving unit improves a testability of the FSM description by reducing an average distance between all pairs of the plurality of states by selecting (112) a center state from the candidate states and providing (113) the FSM description with new transitions, each of which is directed to the center state from each of the plurality of states other than the center state.

Abstract: A method for a logic optimization in a logic synthesis comprises the following steps. Prior to an actual execution of a logic flattening process, a scale of unoptimized circuits is estimated assuming that the unoptimized circuits have already been subjected to the logical flattening. The unoptimized circuits are subjected to a two-level logic optimization only when an estimated scale of the unoptimized circuits exceeds a predetermined threshold value. Prior to an actual execution of a logic flattening process, a scale of the optimized circuits is estimated assuming that the optimized circuits have already been subjected to the logic flattening. The optimized circuits are subjected to the logic flattening if an estimated scale of the optimized circuits does not exceed the predetermined threshold value.