Abstract: In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portion 14 for superposing an OSD signal on the input image signal, and a controlling portion 15. The FRC portion 10 has a motion vector detecting portion 11e for detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portion 11f for allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portion 12d for generating an interpolation frame from the interpolation vector.

Abstract: In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portion 14 for superposing an OSD signal on the input image signal, and a controlling portion 15. The FRC portion 10 has a motion vector detecting portion 11e for detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portion 11f for allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portion 12d for generating an interpolation frame from the interpolation vector.

Abstract: In an image displaying apparatus including a motion compensated rate converting (FRC) portion, deterioration of image quality is prevented in an image having a high-speed region and a low-speed region mixed. The FRC portion includes a motion vector detecting portion 11e and an interpolation frame generating portion 12b. The motion vector detecting portion 11e includes a first region detecting means 112e1 that detects a first region (high-speed region) including a motion amount equal to or greater than a first predetermined amount from an input image signal, a second region detecting means 112e2 that detects a second region (low-speed region) including a motion amount equal to or less than a second predetermined amount from the input image signal, and a third region detecting means 113e that detects a still region from an inter-frame difference of the input image signal.

Abstract: In an image displaying apparatus including a motion compensated rate converting (FRC) portion, deterioration of image quality is prevented in an image having a high-speed region and a low-speed region mixed. The FRC portion includes a motion vector detecting portion 11e and an interpolation frame generating portion 12b. The motion vector detecting portion 11e includes a first region detecting means 112e1 that detects a first region (high-speed region) including a motion amount equal to or greater than a first predetermined amount from an input image signal, a second region detecting means 112e2 that detects a second region (low-speed region) including a motion amount equal to or less than a second predetermined amount from the input image signal, and a third region detecting means 113e that detects a still region from an inter-frame difference of the input image signal.

Abstract: An image display device comprising a frame rate converting (FRC) portion can prevent image degradation at a screen boundary part attributed to the FRC processing when displaying an image obtained by combining a plurality of screens. The image display device comprises an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between frames of the input image signal and a screen combining portion 13 for combining a plurality of screens. When displaying an image obtained by combining a plurality of screens, the screen combining portion 13 combines a plurality of screens by matching a motion detection block boundary when performing the motion compensation process by the FRC portion 10 with the respective screen boundaries of the plurality of screens.

Abstract: In an image display device having a frame rate converting (FRC) portion, it is possible to prevent image degradation of a combined image display portion such as an OSD and PinP attributed to the FRC process. The image display device includes: an FRC portion 10 for converting the number of frames of an input image signal by interpolating an image signal subjected to a motion compensation process between the frames of the input image signal; an OSD processing portion 14 for superposing an OSD signal on the input image signal, and a controlling portion 15. The FRC portion 10 has a motion vector detecting portion 11e for detecting a motion vector between the frames of the input image signal, an interpolation vector evaluating portion 11f for allocating interpolation vector between frames based on the motion vector information, and an interpolation frame generating portion 12d for generating an interpolation frame from the interpolation vector.

Abstract: A three-dimensional image rendering portion, based on image data, performs geometric transformation, projection transformation, etc. and further applies texture data from the texture memory onto polygons, to thereby generate graphic data of a 3-D image. This graphic data is used as pixel data for a frame of image and written into the frame memory. A 3-D texture modeling value generating circuit performs arithmetic operations on 3-D texture modeling values of asperities of the textures, using coordinate data given from the 3-D image rendering portion, bump data stored in the texture memory and parameters stored in the register. These 3-D texture modeling values are provided to 3-D texture modeling circuit where, based on these values, the data from the frame memory is formed into a 3-dimensional form, which in turn is displayed on the display unit.

Abstract: This texture pattern memory circuit is composed of a multi-texture pattern memory, a writing device and a texel selector. The multi-texture pattern memory includes an adder, a subtracter, selectors, 1st to 4th address converting devices, and 1st to 4th memory modules. The texel selector selects only the necessary data from the texel data outputted from the multi-texture pattern memory.

Abstract: A three dimensional sprite rendering apparatus for producing three dimensional graphic images includes a three dimensional graphic circuit for producing backgrounds of three dimensional graphics and outputting pixel data for each pixel of the backgrounds, and a first buffer storing depth data for each pixel of the backgrounds. The apparatus further includes a voxel character control register for storing control data for voxel characters, a voxel character memory storing geometric data for voxel characters, a volume rendering circuit connected to the voxel character control register and the voxel character memory for producing graphics of voxel characters and outputting pixel data for each pixel of the voxel characters, and a second buffer storing depth data for each pixel of the voxel characters.