Abstract: There is disclosed a pressure control valve comprising: a valve body (10A) provided successively with, mentioning from the upstream side in the flowing direction of refrigerant, a refrigerant inflow port (11), a refrigerant introduction chamber (14), a valve seat (13) with which a rod-like valve (15) is retractably contacted, and a refrigerant outflow port (12); and a temperature-sensitive/pressure-responsive element (20) which is provided with a temperature sensitive chamber (25) for sensing the temperature of the refrigerant that has been introduced into the refrigerant introduction chamber (14) and is designed to drive the valve (15) in opening or closing direction in response to fluctuations of the inner pressure of the temperature sensitive chamber (25). The temperature-sensitive/pressure-responsive element (20) is integrally attached to the valve body (10A).

Abstract: An inspection device inspecting for a defect of a semiconductor wafer based on an image of the wafer surface includes an imaging device obtaining image data of a wafer subjected to inspection, a storage circuit storing reference image data of the wafer, an image comparison unit comparing the image data of the wafer subjected to inspection and the reference image data using an inspection condition, an acquiring circuit acquiring wafer in process (WIP) data of the wafer subjected to inspection, and a WIP data operating unit setting the inspection condition based on the WIP data obtained.

Abstract: An inspection device inspecting for a defect based on an image of wafer surface includes an imaging device obtaining an image data of a wafer subjected to inspection, a storage circuit storing an image data of a wafer for comparison reference, an image comparison unit comparing the image data of the wafer subjected to inspection and the image data of the wafer for comparison reference using a pre-set inspection condition, an acquiring circuit acquiring the WIP data of the wafer subjected to inspection, and a WIP data operating unit setting the inspection condition based on the obtained WIP data.

Abstract: A method of testing a semiconductor device is provided. In a SEM image comparison type testing apparatus, a comparison is made between the voltage contrast of a predetermined pattern to be tested and the voltage contrast of a reference pattern to produce a comparison image containing only one of two binary contrast levels. A dimension based on contrast regions in the comparison image is measured, and a characterizing dimension varying depending on the process of manufacture of the semiconductor device is analyzed from the result of measurement.

Abstract: A method of testing a semiconductor device is provided. In a SEM image comparison type testing apparatus, a comparison is made between the voltage contrast of a predetermined pattern to be tested and the voltage contrast of a reference pattern to produce a comparison image containing only one of two binary contrast levels. A dimension based on contrast regions in the comparison image is measured, and a characterizing dimension varying depending on the process of manufacture of the semiconductor device is analyzed from the result of measurement.

Abstract: An apparatus for inspecting a semiconductor device comprises a wafer stage (2), a stage driving unit (3), a charged-particle beam irradiation unit (4), an electronic optical system (11), a charged-particle beam control unit (12), a secondary-electron detection unit (5), an amplifier (7), a secondary-electron intensity comparison unit (8), a database (9) connected to an output of the secondary-electron intensity comparison unit (8), a PC (10) connected to an output of the database (9) and a main control unit (6) connected to the output of the database (9) and an output of the PC (10), whose output is connected to the stage driving unit (3), the charged-particle beam irradiation unit (4) and the charged-particle beam control unit (12). The database (9) stores inspection results and inspection addresses on m inspection regions (15) with strong possibility of having opening failures of contact holes (16) in each of a plurality of semiconductor wafers (1).

Abstract: A valve body 10 of an expansion valve 1 comprises a valve chamber 14 to which refrigerant from a compressor is supplied. The amount of refrigerant is controlled between a valve member 40 and a valve seat 16, and travels through a first passage 20 to an evaporator. The refrigerant returning from the evaporator travels through a second passage 50 and into the compressor. The valve chamber 14 is equipped with a bypass passage which is communicated through a narrow hole 24 to an opening 26 with a bottom, and through a conduit 28 to the first passage 20. The electromagnetic valve 100 comprises a plunger 130, and opens/closes the bypass passage by a pilot valve 150. A pressure switch 220 is equipped to an opening 54 communicated to the second passage 50, and when the pressure of the refrigerant returning from the evaporator is reduced, the valve 100 is operated and the bypass passage is opened.

Abstract: A part of a gate insulation film between a semiconductor substrate and an exposed gate electrode of a semiconductor device is partially and stepwise etched away. A voltage is applied between the semiconductor substrate and the gate electrode in a chemical wet etching system at each step. An anode oxide film is formed on the surface of the gate electrode in a step, when a defect is included in a gate oxide film. The gate electrode is etched away in another step, when a defect is not included in the gate oxide film. A position of a defect in the gate insulation film is detected from the difference in the area of the gate insulation film when an anode oxide film is formed on the gate electrode, and when the gate electrode is etched away.

Abstract: Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors.

Abstract: A non-volatile semiconductor storage device with which a multi-value memory is realized and the amount of information storable is increased without increasing the number of memory transistors and the area occupied thereby. A gate electrode portion 20a of each memory transistor has a two-layer floating gate structure comprising two floating gate electrodes 22a, 22b and a control gate electrode 24 which are substantially vertically laminated one above another. The non-volatile semiconductor storage device is thereby constructed as a multi-value memory capable of providing a state "1" where electrons are injected into the first floating gate electrode 22a, a state "0" where electrons are injected into the first and second floating gate electrodes 22a, 22b, and a state "2" where electrons are withdrawn from the first and second floating gate electrodes 22a, 22b.

Abstract: The method is to selectively etch the etching residue in non-conductive state occurring in semiconductor manufacturing process. A silicon substrate cassette is used in such selective etching.In removing the etching residue in non-conductive state occurring in semiconductor manufacturing process, by applying a positive potential to part of conductive silicon substrates in an etching solution, the contact surfaces between the silicon substrates and the portion electrically connected thereto and the chemical etching solution are anodically oxidized to protect with a passive film, while only the etching residue in non-conductive state is selectively removed by isotropic etching, thereby achieving the purpose.

Abstract: A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).

Abstract: A DRAM having a stacked-type capacitor whose structure has a capacitor lower electrode, a first impurity region connected thereto, a third impurity region formed by thermal diffusion of impurities included in the capacitor lower electrode, is disclosed in which an end portion of a third impurity region on the side of gate electrode can be effectively prevented from being extended from an end portion of a first impurity region on the side of gate electrode in the subsequent heat treatment. In the DRAM, an epitaxial silicon layer 8 or a polycrystalline silicon layer 28 having an impurity concentration lower than that of capacitor lower electrode 9 is interposed between capacitor lower electrode 9 and a first impurity region 3b, so that thermal diffusion of impurities in capacitor lower electrode 9 is reduced as compared with the conventional case.

Abstract: A semiconductor device includes an impurity doped polycrystalline silicon layer formed on a first conductivity type semiconductor substrate with an oxide film provided therebetween, an interlayer insulation layer formed on the polycrystalline silicon layer and provided with a contact hole using the surface of the silicon layer as a bottom surface, and a conductive wiring layer formed on the surface of the interlayer insulation layer and on the inner wall surface of said contact hole. A second conductivity type impurity diffusion layer is formed at a region of the surface of the semiconductor substrate located below the contact hole. A pn junction formed between the impurity diffusion layer and the semiconductor substrate ensures insulation against its reverse bias voltage to prevent leakage current to the semiconductor substrate.

Abstract: A semiconductor device comprising a contact region having reduced contact resistance is provided by the steps of implanting ions of impurities to a predetermined region of a main surface of a semiconductor substrate; forming an impurity diffusion region by applying heat treatment at 400.degree. C.; etching the region from the surface of the semiconductor substrate to the maximum point of an ion concentration to form a metal wiring layer on the exposed surface of the thus formed impurity diffusion region. Since the impurity diffusion region is connected to the metal wiring layer at the maximum point of the ion concentration, the contact resistance can be a low value.