Abstract: An adaptive array communication system includes an adaptive control unit (31) which performs a weighting process by multiplying received signals from a plurality of antennas by complex weights which are different from each other for respective states to combine the received signals, a decoding unit (34) which calculates a metric corresponding to a transition to a desired state, and an error vector calculation circuit (33) which calculates an error vector for calculating complex weights which are different from each other for the respective states.

Abstract: In a communication system using the time diversity transmission scheme, the communication system provided with the stable automatic frequency control circuit with the wide frequency pull-in range and under low CN ratio transmission is achieved by removing the modulation phase from the received data through the application of the data correlation of the time diversity.

Abstract: In the automatic frequency control apparatus, a correlation between a complex spectrum spread signal and a spread code is computed to output a complex correlation signal. A sample clock for sampling the complex spectrum spread signal and a data clock synchronous with a repetitive period of the spread code are generated based on the complex correlation signal. Delay correcting sections correct the delays so that generation timings of the correlation peak values with respect to each parallel transmission signal of each of the complex correlation signals divided to N signals. Latch sections latch the correlation peak value using a data clock and a synthetic frequency error signal generating section for generating a synthetic frequency error signal based on each signal. Frequency offset of the local carrier is corrected based on the synthetic frequency error signal.

Abstract: In the present invention, the amplitude subtracting type of phase detector of the timing recovery section outputs a difference &ggr;i of a synthesized amplitude deviation at ½ of a symbol time. The averaging section computes an average value of this difference &ggr;i and outputs a phase control signal Vi corresponding to the average value to the phase controller. The phase controller controls a timing phase of the sampling clock according to this phase control signal Vi. Dichotomizer generates a recovered symbol clock by dichotomizing the sampling clock that has been timing phase controlled. Removal of DC offset from and demodulation of the sampled baseband signal is executed in parallel to the above processing using the recovered symbol clock with the Nyquist data extracting section, the offset detector, the offset correcting section, and the data determining section.

Abstract: An automatic frequency controller includes a frequency offset estimating section that calculates phase distortion quantities and the average thereof from known signals contained in a received signal. The frequency offset estimating section obtains, from the average distortion quantity, signal powers corresponding to a plurality of candidate frequency offsets set at frequency offset estimation accuracy intervals in a frequency offset estimation range. The frequency offset estimating section looks at the signal powers through a frequency window with a frequency width corresponding to a transmission path state. This makes it possible to maximize the signal power of a frequency of a radio wave or radio waves corresponding to the transmission path state, and to place the radio wave or radio waves corresponding to the transmission path state as a frequency controlled object. This can improve demodulation accuracy.

Abstract: An adaptive array communication system includes an adaptive control unit (31) which performs a weighting process by multiplying received signals from a plurality of antennas by complex weights which are different from each other for respective states to combine the received signals, a decoding unit (34) which calculates a metric corresponding to a transition to a desired state, and an error vector calculation circuit (33) which calculates an error vector for calculating complex weights which are different from each other for the respective states.

Abstract: In a DLL, in-phase correlation signal and orthogonal correlation signal are squared and adder to generate correlation power. Delays are provided so that the peaks of N number of divided correlation power portions to have coincided timing with each other. Composite correlation power is generated from the respective correlation power portions. A composite error signal of a sample clock is generated by subtracting the composite correlation power from the composite correlation power that has been delayed. A data clock is generated by frequency-dividing the sample clock based upon an acquisition pulse. A sample clock is finally generated based upon the composite error signal that has been latched and noise-removed therefrom in synchronized timing with the data clock that has been delayed.

Abstract: Two A/D converters sample received base band signal Sb by asynchronous sampling clock at double speed of symbol rate, and based on the sampled data series Ii, Qi. A transmission complex symbol frequency generator generates data series Ei, Di of transmission complex symbol frequency component. A correlation value calculator outputs correlation data series SMi as the correlation value of cosine wave data series Ci, and data series Ei, D1 of symbol frequency generated by a cosine wave generator, based on the asynchronous sampling clock CK. An inverse tangent calculator outputs a timing error &tgr; based on the correlation data series SMi.

Abstract: A demodulator in a receiver has a multiple symbol differential phase detector which calculates phase differences between a received signal and received signals of 1, 2, . . . , N (Where N is an integer greater than 2) before so as to output the calculated results as N symbol differential phase detected signals. Further, a soft decision sequence estimating unit in this demodulator estimates a transmitted differential phase sequence according to the 1, 2, . . . , N symbol differential phase detected signals using a trellis diagram representing transitions of differential phase states of a transmitted signal and Viterbi algorithm and estimates soft decision demodulated data according to estimated transmitted differential phase sequence and the survival path metrics that transit into each state on the trellis diagram.

Abstract: In the identical spread code multiplex SS system, a delay correction unit and a multiplexer calculates the multiplexed square correlation value by matching the peak values and adding the square correlation values of all the multiplexed signals. The multiplexed signals are the signals obtained by multiplexing an RF signal in such manner that different specific delay times are respectively given to parallel transmission information sequences multiplied by identical spread codes. Therefore, code synchronization can be realized by using only one correlator for both the orthogonal and an in-phase components.

Abstract: A phase region deciding unit decides the phase region in which the signal point falls and a counter unit counts the number of signal points in each phase region. A weighted average calculating unit calculates a weighted average using the previous weighted average and a result of counting in the counter unit. A likelihood calculating unit calculates likelihood of the weighted average of phase distribution calculated weighted average using the phase-distribution table stored in a phase-distribution table storing unit for each phase-distribution model, detects a maximum likelihood phase-distribution model, and outputs the signal quality corresponding to the detected phase-distribution model as the estimated signal quality.

Abstract: In the communication system using the binary phase shift keying (BPSK) modulation method, an erroneous data that might be caused by a carrier slip of carrier wave generated during coherent detection can be compensated. The modulation unit of the transmitter transmits identical data at differentiated timing through BPSK modulation, and the coherent detector circuit of the demodulation unit of the receiver detects waves upon receiving signals. The compensating circuit makes time differences in transmitted data equal and compares them to detect mismatch in order to compensate carrier slip found in the received signal and then the combination circuit realizes the combination.

Abstract: According to the present invention, it is possible to improve a bit error rate performance of a conventional diversity receiver.In a diversity receiver of the present invention, first, second to Lth multiple differential detection signals and received signal strength are generated by multiple differential detection/signal strength detecting circuits, and are inputted into a combined branch metric generating circuit in a sequence estimator, thereby generating a combined branch metric. An ACS circuit is operated for an ACS operation on the basis of Viterbi algorithm by using the combined branch metric. A path memory sequentially takes as input path selecting signals outputted from the ACS circuit, and update the memory contents. A maximum likelihood state detecting circuit detects the most probable state by using a path metric outputted from the ACS circuit.

Abstract: A synchronization determining method and circuit for determining a synchronization state of a multiplexed data stream derived by multiplexing a plurality of data streams having the same contents with a time lag provided therebetween, wherein the synchronization determining circuit establishes synchronization without decreasing transmission efficiency, generating incorrect code sequences, or increasing overall circuit scale. In each embodiment of the present invention, synchronization is established without using synchronization words. Because synchronization is achieved without feedback loop delay, incorrectly decoded sequences are not generated for a period of time before synchronization is established. Also, because no maximum pass metric state detecting circuit is required, circuit scale, power consumption, and operating speed can be improved.

Abstract: A receiver, an automatic gain controller suitable for the receiver, a control signal generator suitable for the automatic gain controller, a reception power controller using the automatic gain controller and a communication method using the receiver. The instantaneous power of a received signal output from a variable gain amplifier or attenuator is detected by a power detector. The detected instantaneous power is quantized by a comparator and filtered through a random walk filter. An up-down counter counts up or down in accordance with the increment signal or the decrement signal obtained by filtering. In this manner, error in the gain control of the variable gain amplifier or attenuator is obtained.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A complex baseband signal as long as one period of PN signal is divided into three sequences. The three partial signals are input to three correlators which then calculate the correlations between the three partial signals and three partial PN signals. The squares of the absolute values of outputs from the three partial correlators are summed and the peak of the resultant summed signal is detected, thereby performing initial acquisition and tracking of synchronization of PN signal. Outputs from the three partial correlators are added together by an adder for generating a correlation signal used for data demodulation. Since partial correlation signals output from three partial correlators have a phase difference corresponding to a frequency offset, and error signal corresponding to the frequency offset is provided by performing complex conjugate product operations on the partial correlation signals.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.